As device dimensions continue to scale down into the deep submicrometer regime, there is an increasing challenge for fabricating robust gate dielectrics with low susceptibility to process-induced device degradation and a continuous motivation for the exploration of new options for thin gate dielectrics. This work assesses a variety of gate stack processing techniques as alternatives to conventionally furnace grown gate oxides in the context of a tenth-micron technology, which features LOCOS isolated, two-implant channel, NMOS transistors fabricated with a 3.0 nm thick gate dielectric, 0.15 μm thick polysilicon gate, implanted extension- and contact-junctions of 20 and 50 nm deep, respectively, and effective channel lengths down to 0.12 μm, operating at 1.2 volts. The alternative deposition and oxidation techniques include furnace oxynitride formation, rapid-thermal oxidation (RTO), rapid-thermal chemical vapor deposition (RTCVD) and plasma-assisted chemical vapor deposition (RPECVD). Compared to the 0.25- and 0.18-μm technological nodes, the thermal budgets associated with gate oxide formation are dramatically lower and their impact on channel dopant redistribution is not as strong as in previous technologies. Negligible polysilicon depletion effects were observed in the fabricated devices (Cinv/Cox = 97%). Drive currents and threshold voltage control comparable to furnace oxides were achieved by alternative gate-stack processing techniques.

The quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

Scaling of MOS devices is projected to continue down to device dimensions of at least 50 nm. However, there are many potential roadblocks to achieving such dimensions and many standard materials and front-end processes which must be significantly changed to achieve these goals. The most important areas for change include (a) gate dielectric materials, (b) gate contact material, (c) source/drain contacting structure and (d) fundamental bulk CMOS structure. These projected changes are reviewed along with possible applications of rapid thermal processing to achieving future nanometer scale MOS devices.

In order to prevent boron penetration in PMOS transistors without degrading channel mobility, it is necessary to engineer the distribution of nitrogen introduced into the gate oxide. We have investigated methods of engineering this distribution using nitric oxide (NO) gas in an RTP system to thermally nitride ultra-thin gate oxides. In one approach, the gate oxide is simultaneously grown and nitrided in a mixture of nitric oxide and oxygen. For a 40 Å film, SIMS depth profiling shows that this process moves the nitrogen peak into the bulk of the oxide away from the oxide silicon interface. In another approach, an 11 Å chemical oxide produced by a standard pre-furnace wet clean is nitrided in NO at 800 deg. C. This film is subsequently reoxidized in either oxygen or steam. For an 1100 deg. C., 120 sec RTP reoxidation in oxygen, the final film thickness is 41 Å. The nitrogen has a peak concentration of 5 at. % and the peak is located in the oxide 25 Åfrom the oxide/silicon interface. Ramped voltage breakdown testing was carried out on MOS capacitors built using reoxidized NO nitrided films. They have breakdown characteristics that are equivalent to conventional furnace grown oxides. These films show considerable promise as gate dielectrics for CMOS technologies at geometries of 0.25um and below.

This paper describes a novel synthesis route for producing defect-free siliclon nitride films that are demonstrated to provide state of the art electrical performance in MOS devices with stacked oxidenitride gate dielectrics in both nmos and pmos devices. High concentrations of bonded hydrogen are introduced into the as-deposited nitride films during a 300°C remote plasma-enhanced deposition, and then the majority of this hydrogen is evolved during a 30 second rapid thermal anneal (RTA) at 900°C. The nitride formed in this way is effectively “defect-free” and qualitatively different from nitride films formed by conventional chemical vapor deposition processes.

BST/TiO2/(Barrier Layer) stacked dielectric structure has been proposed for ultra thin (<20Å) gate dielectric application to overcome the direct tunneling current problem of Si02. To characterize the alternative dielectrics, MIM and MIS capacitors were fabricated. TiO2 is believed to prevent BST and Si from reaction and interdiffusion while TiC2 itself is stable due to the strong binding energy. For better interfacial quality of TiO2/Si interface, proper barrier layer is needed between TiO2 and Si. Optimization of this barrier layer was performed by RTP grown N20 oxide and self-grown interfacial oxide layer with various annealing conditions. To monitor these barrier layers, TEM and electrical analysis were performed. From TEM observation, it was found that interfacial layer was formed in every sample whether it was intentionally grown or not. It was observed that the leakage current of Pt/TiO2/Si dramatically increased after 700'C or higher temperature annealing. This might be related to the transition of crystal structure of TiO2 from anatese to rutile at about 700°C[1]. It was also found that both Pt/BST/TiO2/Si and Pt/TiO2/Si showed lower leakage current compare to the conventional NO oxide at comparable equivalent SiO2 thickness. These results imply that these materials hold some promise as alternatives of pure SiO2 in very thin range.

A study was performed using a combination of in-situ real time ellipsometry and atomic force microscopy (AFM) to follow the RTCVD process in real time and measure key nucleation parameters in an effort to elucidate the mechanism of Si nucleation on SiO2. Real time ellipsometry data, in terms of delta versus time, showed significant changes as the deposition evolves from critical nuclei through coalescence to continuous film growth thereby allowing. process monitoring and control. From the AFM images, nuclei parameters such as nuclei height, radius, and density were collected and compared across processing temperatures. It was found that kinetic factors control the growth process resulting in a transition temperature (660°C) where the size, shape, and density of the nuclei abruptly changes from small numerous nuclei to large, sparse disk-like nuclei.

In this work, in-situ doped polysilicon and poly-SiGe films have been used as the gate material for the fabrication of MOS devices to evaluate their respective performances. These films were deposited in an RTCVD system using a Si2H6 and GeH4 gas mixture. MOS capacitors with 45 Å thick gate oxides and polysilicon/poly-SiGe gates were subjected to different anneals to study boron penetration. SIMS analysis and flat band voltage measurements showed much lower boron penetration for devices with poly-SiGe gates than for devices with polysilicon gates. In addition, C-V measurements showed no poly depletion effects for poly-SiGe gates while polysilicon gates had a depletion effect of about 8%. A comparison of resistivities of these films showed a low resistivity of 1 mΩ-cm for poly-SiGe films versus 3 mΩ-cm for polysilicon films after an anneal at 950 °C for 30 seconds.

We have fabricated polycrystalline Sil-x-yGexCy by Rapid Thermal Chemical Vapor Deposition and used it as part of a polycrystalline gate structure for PMOS devices. The results showed that the use of carbon in polycrystalline Sil-x-yGexCy suppressed boron penetration across the gate oxide. No effects of gate depletion with the use of poly-Sil-x-yGexCy were observed. Our work suggests that the addition of carbon reduced the chemical potential of boron in Sil-x-yGexCy, which deterred boron from diffusing across the underlying gate oxide.

The chemical stability of the compound metals TiNx and WNx on SiO2 and SiO2/Si3N4 (ON) dielectric stacks is studied by on-line Auger electron spectroscopy (AES) following sequential rapid thermal annealing treatments of 15 - 180 s up to 850 °C. The TiNx/SiO2 interface reacts at 850 °C and the reaction is kinetics driven. The TiNx/Si3N4 interface is more stable than TiNx/SiO2 even after a 180 s anneal at 850 °C. WNx is stable below 650 °C both on SiO2 and Si3N4, but above this temperature the film changes, possibly due to crystallization or interdiffusion. The changes in the WNx film are not controlled by kinetics. The compound metals are chemically more stable at elevated temperatures than pure Ti or W on SiO2.

The effects of ramp-up rate during rapid thermal processing of ultra-shallow boron implants have been investigated. Ramp-up rates were varied between 25 °C and 200 °C for two types of anneals: soak anneals and spike anneals. It was found that the ramp-up rate had very little influence on junction depth or electrical activation for both types of anneals. Spike anneals did produce shallower profiles than soak anneal for a comparable electrical activation and may be an option for future processes.

Rapid Thermal Annealing (RTA) is indispensable for the formation of ultra-shallow source/drain junctions. To improve the annealing conditions, a fundamental understanding of the influences on the diffusion/activation process is necessary. Ion implantations of 1 keV boron at a dose of Φ≈1 I.1015 cm-2 are annealed in a SHS2800E RTP-system under controlled concentrations of oxygen in nitrogen ambient (0-1 ppm up to 1%). Concentration-depth profiles, measured by Secondary Ion Mass Spectroscopy (SIMS), are simulated within the framework of the kickout model involving diffusion enhancement via supersaturation of silicon self-interstitials. The validity of this interpretation is supported by the simulated results which are in good agreement with expenimental data. After RTA for 10 s at 1050°C the junctions are varying within a range of 800Å to 1400Ådepending on the annealing ambient. The results of the simulation yield finite values of self-interstitial supersaturation as a function of the oxygen concentration.

2 keV to 10 keV arsenic, As+, and arsenic dimer ions, As 2 +, were implanted into silicon at a dose of le15 cm-2 and 3e 15 cm-2 at 0° and 7°' tilt angles. For bare wafers, a low concentration of oxygen is required to provide sufficient capping during anneal to minimize out-diffusion. In the presence of oxygen, enhanced diffusion occurs during the anneal, the extent of which is a function of the concentration of oxygen and the temperature of anneal. The oxidation enhanced diffusion (OED) is significant at anneal temperatures above 1050°C. The extent of OED is observed to be more significant for the samples with lower energy As+ implants. An alternative technique for minimizing OED, without much out-diffusion, is the use of higher energy, 5 keV implants through a screen oxide. For identical anneal conditions, 5 keV As+ implants through a 40 Å screen oxide offer junction depth and sheet resistance values equivalent to that of 2 keV implants into bare silicon. As the screen oxide is sufficient to cap the out-diffusion of dopants, a nitrogen ambient or a lower temperature could be employed to get shallower junctions without much degradation in the sheet resistance. Further reduction in junction depths can be achieved by using the As 2 + implants.

Ion implants of 1.0 keV 11B+, 5 keV BF 2 +, and 2.0 keV As+ at a dose of IeI5/cm2 were rapid thermal annealed (RTA) in a STEAG AST-2800µ with varying percents of oxygen in N2, ranging from 0-lppm to 50,000 ppm to investigate the effects of low concentrations of oxygen during anneal. Sheet resistance (Rs), ellipsometry, SIMS, Tapered Groove Profilometry (TGP), and Scanning Force Microscopy (SFM) were employed to characterize these layers. For each of these implant cases, an optimal RTA condition is established which maximizes retained dose while still producing shallow junctions. As a function of O2 content, anneal temperature and implant condition, three regimes are observed that affect after anneal retained dose. These regimes are: dopant loss to the ambient resulting from etching of Si, dopant loss by out-diffusion from evaporation/chemical reactions, a capping regime that minimizes out-diffusion. In this later regime the dopant loss results from consumption into the RTA grown oxide. In addition, this paper also discusses oxidation enhanced diffusion (OED) and identifies its extent as a function of temperature and O2 content of the anneal for the three implant conditions investigated. For example, a 1.0 keV 11B+wafer annealed at 1050°C lOs in a controlled 33 ppm of O2 in N2 yields a SIMS junction depth 320 Å shallower than previously reported by others.

In this paper we examine several applications of Rapid Thermal Chemical Vapor Deposition (RTCVD) for the fabrication of sub-100 rum MOSFET's. Vertical dual-gated MOSFET’s are used as a test vehicle to implement FET's of very short channel length. To realize such devices, the ability of epitaxial Si1-x-y, GexCy layers for suppressing the thermal diffusion, transient enhanced diffusion, and oxidation enhanced diffusion of boron both in the Si1-x-y, GexCy and in nearby Si layers is very useful Novel gate electrodes deposited by RTCVD also showed the ability to greatly reduce boron penetration in ptype polycrystalline gates for p-channel FET’s.

A low-thermal budget, in-situ boron doped silicon epitaxy process for channel engineering and ultra shallow junction formation is presented. Ultra-thin silicon films (100–500 Å) have been deposited in a single-wafer Ultra High Vacuum Rapid Thermal Vapor Deposition (UHV-RTCVD) reactor using disilane (Si2H6), diborane (B2H6), and chlorine (Cl2) at temperatures between 750- 800°C. Boron doping can be varied five orders of magnitude (1016 cm-3 1021 cm3) with very abrupt doping transitions (∼50–70 Å/decade). Short channel (Leff =0.12 /μm) lightly-doped nchannel MOSFETs have been successfully realized free of ion-implantation in the channel region. As another application, ultra-shallow, defect-free, abrupt junctions (<500 Å) through diffusion from selectively-deposited in-situ boron doped films have been demonstrated.

A facet-free, selective epitaxy process has been identified using the SiH2CI2 /HCI/H2 chemistry in a commercially available, single-wafer epitaxy reactor. The pre-epitaxy bake required a minimum of 900°C in order to obtain a clean silicon surface with reasonable throughput while preserving the integrity of the shallow trench isolation structures. The epitaxy growth rate ranged from as low as 130Å/rnin at 825°C, 10 torr to as high as 1500 Å/min at 875°C and 70 torr while the deposition rate of polysilicon on polysilicon differed significantly: at 10 torr, the epitaxy growth rate is greater by as much as 50%, and at 70 torr the polysilicon deposition rate is greater by as much as 40%. The facet suppression depended heavily on two things: the undercut beneath the polysilicon gate sidewall insulator and the process pressure. The undercut is believed to be responsible for suppressing the initial stage of facet formation, most probably by completely eliminating lateral overgrowth of the crystal. The process conditions then enable continued facet suppression perhaps by restricting the silicon surface mobility. The sidewall structure and process conditions combine to make a reliably facet-free selective epitaxy process

The introduction of rapid thermal processing for silicide formation has triggered a lot of research to temperature uniformity and reproducibility in RTP systems. In addition to the temperature, the ambient control is to be taken into account. Although gasses are specified to a low level of contaminants, the RTP step needs to be optimised for optimal contaminant reduction. Besides, the process wafer itself is a source of contamination.

In this paper an overview will be given of the role of RTP ambient on the silicidation processes. The effect of the wafer on ambient purity will be highlighted. It will be shown that the use of a reactive capping layer during silicidation represents an adequate solution for both sources of contamination.

In this work we describe the formation of ultra-thin PtSi layers using sputtering for metal deposition and RTP for the silicidation. The problem associated with the controllability of deposition of ultra-thin metal layers can be circumvented by depositing a thick Pt layer followed by a 2-step RTP process with a selective etch step in between. Continuous and uniform 3 nm thick PtSi layers are formed with this technique. Moreover, in another approach similar to the previous one, but in which the first RTP step is omitted, a much smoother PtSi layer is formed. The importance of the interfacial Pt/Si layer formed during metal deposition is described. These processes are totally compatible with CMOS technologies, as shown below.

A novel low temperature self-aligned Ti silicidation with Ge+ pre-amorphization implant (PAI) is presented. Compared to conventional high temperature PAM silicidation, the advantages of Ti salicidation at temperatures below the recrystallization of a pre-amorphized layer are: (1) C49 TiSi2 silicide formation occurs only in the pre-amorphized layer so that the silicide depth can be well controlled, forming a very sharp interface between the silicide and the Si substrate; (2) Ti just reacts with the amorphous layer, avoiding the so-called bridging issue in which the silicide grows laterally over the isolation or spacer; (3) the effects of metal thickness and substrate doping on silicide formation are suppressed.