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Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

Published online by Cambridge University Press:  10 February 2011

A. Srivastava ,
H. H. Heinisch ,
E. Vogel ,
C. Parker ,
C. M. Osburn ,
N. A. Masnari ,
J. J. Wortman  and
J. R. Hauser
A. Srivastava
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
H. H. Heinisch
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
E. Vogel
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
C. Parker
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
C. M. Osburn
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
N. A. Masnari
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
J. J. Wortman
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
J. R. Hauser
Affiliation:
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606.
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Abstract

The quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 525: Symposium W – Rapid Thermal & Integrated Processing VII , 1998 , 163
Copyright
Copyright © Materials Research Society 1998

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References

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