Infiltration of anodically prepared porous silicon with tungsten hexafluoride gas has been investigated as a function of silicon porosity, source gas pressure and carrier gas type and flow rate. The depth of tungsten metallization in the silicon has been shown to depend most sensitively on the WF, partial pressure, and less on the flow rate and carrier gas type. Penetration depths of 30 pirn have been attained. Structural integrity of the tungsten layer is dependent on the porosity of the starting material and the degree of internal oxidation of the porous silicon surface area.

In this paper the various performance advantages of SOI and SOS structures for submicron ULSI circuits will be described. In addition to the traditional speed and radiation-hardness advantages, there are several significant advantages of thin-film SOI compared to bulk structures for the submicron scaling of MOS transistors. These advantages include short-channel threshold voltage stability, improved sub-threshold slope, increased saturation current, and reduced hot electron effects. Both theory and data from several groups will be presented to illustrate these effects. Since these advantages all fall in areas that are critical limits to device engineering and scaling in the submicron regime, the motivation for using SOI should be even stronger as devices are scaled to smaller dimensions in the future. Consideration of SOI or SOS on the ULSI scale will require a technology capable of low defect films with a film thickness of 1000 A or less, however. The prospects for minority carrier devices such as bipolar transistors for BI-MOS will also be discussed. Both device structure (lateral vs. vertical) and material quality are issues that must be addressed.

In the past couple of years, buried oxide SOI has emerged as the leading SOI approach. Significant advances have been made in the understanding and the preparation of the buried oxide substrates. Various VLSI circuits have been demonstrated with excellent results, proving the maturity and the manufacturability of this technology. In this paper, buried oxide material properties, device parameters and the implementation of a 2.5 urn 4K SRAM and a 1.25 pm 16K SRAM on the buried oxide substrates are reviewed.

Total dose, dose rate, transient, single event upset and neutron radiation effects for dielectrically isolated MOS devices on S01(silicon-on-insulator) substrates are discussed. For large-scale, high-speed circuits, material, layout and process characteristics optimized for high circuit yield and reliability may conflict with improvements required to extend radiation thresholds. Some radiation hardening techniques applicable to silicon-on-insulator high speed thin film MOS devices are presented.

In ionizing-radiation environments, oxide charge buildup in the buried oxide of SIMOX SOI material causes an increase in the back-channel leakage current, resulting in an instability in electronic circuits formed on SIMOX wafers. We report the measured distributions of radiation-induced oxide charge density in buried oxides formed by oxygen implantation. These are obtained by etch-back experiments including C-V measurements using a mercury probe and ellipsometer measurements. The results show a region of higher charge density about 1500A from the top interface with a lower density region within a few hundred angstroms of the top interface. The results also show that the oxide charge density decreases with annealing temperature. Some unusual optical properties of SIMOX oxide observed in ellipsometer measurements are discussed comparatively with thermal oxide.

As-deposited polycrystalline silicon and argon ion laser recrystallized silicon thin film transistors (TFT's) have been fabricated on Corning Code 1729 glass substrates. This novel aluminosilicate glass has an expansion coefficient matched to that of silicon and a chemical durability comparable to that of fused silica. N-channel enhancement mode transistors were made using conventional IC device fabrication procedures (including thermal oxidation to form the gate insulator) modified to have a maximum processing temperature of 800 C. The- polycrystalline silicon TFT's exhibit leakage currents of less than 2x10-11 A/ μm; of channel width and good stability and reproducibility. Transistors made in the recrystallized silicon show field effect electron mobilities as high as 270 cm2/V s, approximately 15 times the mobility of comparable devices made in as-deposited polycrystalline silicon. The recrystallized silicon devices also exhibit lower threshold voltages and lower leakage currents than do the comparable polycrystalline silicon devices. Major advantages of this TFT technology include the use of a novel, potentially low cost glass substrate and the simultaneous processing of both polycrystalline and recrystallized silicon devices on the same substrate material. This approach represents a new avenue for the incorporation of active devices into a variety of applications including integrated active matrix displays.

Adequate techniques for the electrical characterization of SOI structures are reviewed and applied to reveal a coherent image of SIMOX material. Sheet resistance, low temperature Hall effect and photoconductivity measurements are analysed with respect to the processing conditions. Depth profiles are identified by spreading resistance, MOS-Hall devices and differential ellipsometry. After annealing at high temperature the activation of thermal donors, not new donors, is attenuated. The properties of front and buried interfaces are compared with each other and referred to implantation and annealing conditions. The measurements of the dynamic transconductance, charge pumping current and noise in MOSFET's are shown to provide easier and more relevant evaluation than conventional MOS capacitance techniques. The minority carrier generation is studied by separating the contributions of the volume, interfaces and sidewalk. Not only is the performance of transistors fabricated on SIMOX excellent, but additional gain is possible using the new concept of volume inversion.

The use of ultrathin SIMOX wafers for fabricating submicrometer CMOS integrated circuits is described. It is demonstrated from ring oscillator speeds that properly designed devices can exhibit very high transconductance and performance superior to circuits using bulk Si.

A technique is described for performing MOS capacitance-voltage (CV) measurements on thin Si films on insulating substrates. Such measurements are complicated by the lack of a back contact in SOI structures. Design considerations for an MOS capacitor geometry appropriate for this material were made by treating the structure as a distributed RC circuit. Based on these calculations, a structure has been designed and fabricated that permits both high and low frequency CV measurement and analysis. Use is also made of the Si substrate wafer as a back gate both to provide a back channel for front-gate CV measurements and to characterize the back interface. CV measurements and interface state calculations are presented and compared for SIMOX and laser-recrystallized materials. The experimental results are compared with those of numerical solutions to Poisson's equation.

A fast simulation tool for MOS/SOI process optimization has been developed.lt solves Poisson's and one carrier current density equations in the one-dimensional case. NMOS and PMOS transistors characteristics in the linear region are reliably computed over a wide range of voltages. Moreover, special attention has been paid for threshold voltage (calculated by extrapolating the inversion charge as a function of front gate voltage ) and subthreshold current calculation. Therefore, process parameters can be easily selected in order to get enhanced device capabilities.

Of the numerous requirements for advanced VLSI silicon microelectronics, power dissipation per unit area, speed, packing density and radiation hardness are especially important. Power dissipation and speed have forced an evolutionary path from PMOS to NMOS to NMOS E/D and to the currently used CMOS. As evidenced by the large number of publications, CMOS on an insulating substrate is receiving increased attention due to its potential as the next generation in MOS evolution. We review results of our previous and current research in silicon on sapphire (SOS) which has led to high quality ultrathin SOS (<100 nm thick) appropriate for high density CMOS circuitry. Basic materials developments, device performance, and CMOS design considerations in 100 nm thick improved SOS will be discussed.

The material improvement of silicon on sapphire by rapid thermal annealing (RTA) is investigated as a function of the maximum temperature during the RTA cycle. Dramatic improvement of the crystalline quality throughout the silicon epilayer occurs for the lowest RTA temperature used (1160°C). The dechanneled fraction at the surface, Xo = 0.033, for the highest temperature anneal, gives bulk-like silicon values. Thus, at the surface, the crystalline quality is like bulk silicon. For the higher temperature anneals, transmission electron microscopy reveals that only a few microtwins extend to the surface. The defect microstructure in the region of the silicon/sapphire interface is substantially reduced. The RTA results in Al autodoping on the order of 1017 cm-3. The strain in the silicon epilayer is the same both before and after the RTA. The defect elimination can be explained in terms of the motion of the incoherent boundaries of the microtwins.

The effect of predeposition substrate annealing has been investigated for MBE grown silicon films on sapphire substrates (SOS). Films of varying thickness were grown on substrates which had been annealed at either 1450°C or 900°C. The surface morphology and crystal1inity for each film were examined. The silicon thicknesses ranged from 65-400 angstroms and the anneal time for both temperatures was 30 minutes.

The results indicate that the predeposition anneal of the sapphire substrate has a dramatic effect on the growth characteristics of the silicon film. The high temperature anneal promotes island growth of the silicon film which is easily resolved in the SEM. These islands are roughly 800 angstroms wide for a 65A thick film and grow to approximately 2200 angstroms for a 250A film. On the other hsuxi, the lower temperature anneal did not result in island formation, when examined by SEM, at any of the film thicknesses. In addition, X ray analysis reveals that the silicon layers for the high temperature anneal are epitaxial with a (100) orientation.

From a series of imaging experiments performed in the transmission electron microscope (TEM), it is apparent that for silicon grown on sapphire (SOS) by molecular beam epitaxy (MBE), silicon thin film growth on the (1012) sapphire plane resembles that observed for analogous films grown by chemical vapor deposition (CVD). At 900°C very thin (150A) silicon films grow as islands with either the (001) or (110) planes parallel to the (1012) plane; it is also found that most of the silicon grows as (001) rather than (110) islands, as is true for CVD-grown SOS. The orientation, however, of (110) islands occuring in this MBE-grown SOS sample differs from that of (110) islands occuring in CVD-grown SOS. By following this initial 150A of growth with 2500A of silicon deposited at. 750°C, a continuous (001) film was grown in which microtwins appear to be the predominant defect. The MBE-grown SOS also resembles that grown by CVD in that the microtwin densities associated with the “majority” and “minority” twinning systems are influenced by the orientation of the sapphire substrate.

For the crystal orientation control of multi-layered SOI (Silicon on Insulator) by the laser recrystallization technology, the shape and size of seeds were investigated. By utilizing dot seeds less than 3μm square instead of a line seed, the crystal orientation control of a SOI layer was successfully realized without causing evaporation of silicon. Moreover, the dot seed method enabled us to control the crystal orientation of multi-layered SOI by virtue of small heat flow through seed regions.

In the mean time, it was proved that the SOI crystal orientation gradually rotated as the crystal propagated away from the seeds and that the degree of rotation in the second SOI layer was smaller than that in the first one.

This paper describes cross-sectional transmission electron microscopy (TEM) observation on finished 3-D MOS devices, fabricated with a laser-recrystallized SOI. The laser-recrystallized SOI contained crystal defects such as micro-twinning, grain boundaries and dislocations. It is also clearly shown that the interface roughness between the gate oxide and SOI is as much as 20 nm height, in where the interface is very smooth between the gate oxide and bulk silicon.

The surface morphology of SOI has been studied. The surface is very wavy and contains protrusions. Crystal orientations for SOI without protrusions were close to (100), while those for SOI with protrusions were close to either (111) or (101). The angle of orientation rotation for SOI without protrusions was less than 5 degrees over a 600um long SOI stripe, while the angle of SOI with protrusions was about 30 degrees. Threshold voltages of pMOSFET with protrusions in the channel were generally larger than those without protrusions in the channel.

We report the application of a stress-relief technique aimed at reducing the density of dislocations and subgrain boundaries in laser-recrystallized Silicon-On-Insulator (SOI) material. By providing alternate mechanisms for relieving the stresses responsible for defect generation in the Si film, it is possible to exercise a large degree of control over the subgrain boundary density. Large areas of SOI material completely free of dislocations and subgrain boundaries have been obtained by inserting a low-viscosity layer under the silicon film and using an appropriately shaped cw laser beam as the heat source. During the process of zone-melt recrystallization this layer softens and provides an alternative stress relief mechanism, thus reducing the mechanical constraint on the growing crystal. Several examples of subgrain boundary control are described, which have resulted in crystalline regions in excess of 300 μm by several millimeters completely free of low-angle grain boundaries and dislocations.

A novel material SOM (Silicon on Metal) was obtained by laser recrystallization. 0.5miti amorphous-Si film was deposited by glow discharge on a metal substrate covered with lym CVD Si02 Boron ions were implanted in a-Si at an energy of 60KeV and a dose of 5xl015cm-2. A CW argon laser was used to recrystal-lize a-Si film. After CW argon laser irradiation, a-Si was recrystallized and the grain size was increased to 10x40ym, the concentration profile of impurities became uniform and the electrical properties of SOM were improved significantly, sheet resistance lower than 60Ω/⃞n was obtained. The gauge factor of recrystallized SOM materials measured by a cantilever transducer was higher than 30. The devices made of this material have pressure sensitivity of 6mV/V for pressure range 1 bar.

Porous silicon lends itself to a variety of applications due to its unique characteristics such as an interconnected pore network, large surface area, and dopant-dependent selectivity of formation. Although the best-known application of porous Si is for silicon-on-insulator (SOI) fabrication, the porous silicon technique also offers elegant approaches for silicon-on-conductor (SOC) fabrication.

In this paper, we present an overview of porous Si techniques for both SOI and SOC applications. Possible limitations of the oxidized porous silicon process, for SOI in particular, are discussed. We also consider novel and multilayered structures which might be obtained using porous silicon.