Often encountered in the literature dealing with label-free biosensing technologies are sensors made of semiconductor nanowires, silicon nanowires in particular. Since semiconductor nanowires are compatible with CMOS technology, they are often considered as ideal devices to detect chemical and biological elements, including DNA, viruses, and cancer markers for instance. The principle of operation and and the architecture of these nanowires are very similar to the gate-all-around junctionless FETs, except that there is no solid-state electrode over the gate insulator. These nanowires have no source/drain implant and are highly doped i.e., they are fabricated with minimal technological steps. In addition, they exhibit a high surface-to-volume ratio. These features explain why they are seen as the ultimate devices for label-free detection of ions, nucleic acids, and protein markers to say the least. More generally, nanowire FETs can be configured as highly sensitive biosensors by linking recognition or receptor molecules to their surface [189]. However, despite being used in many “bio” applications, analytical models simulating the intrinsic characteristics of such ungated nanowires are missing. Extending the approach presented in Chapter 3 by including additional features to predict the electrical properties intrinsic of semiconductor nanowires when used as biosensors [190] is the goal of this chapter.

Principle of Semiconductor-based Field-Effect Biosensors

The electrostatic interaction between a solution containing chemical species (ions, biomolecules, etc.) and the gate electrode of a field-effect transistor is a topic of interest in the molecular processes of biology. At the beginning was the so-called ion-sensitive field-effect transistor (ISFET) proposed by Bergveld in the 1970s [191]. This device was aimed at measuring ion activities in electrochemical and biological environments and in particular the action potentials that build up during neuronal activity. An overview of ISFET technology can be found in [192–195] and a typical representation is shown in Figure 13.1 [192]. The principle of operation relies on the modification of the charge density between a liquid and an ion-sensitive gate, which induces variations in the drain current.

When immersing an insulator (silicon dioxide) in an electrolyte, a transition layer is created at the interface between the silicon dioxide and the liquid.

The junction field-effect transistor (JFET, also called the JUGFET or junction unipolar gate FET) is the first field-effect device produced before being supplanted by the MOSFET. Even today though its use is limited, the JFET is still used in specific low-noise applications and in new applications in power electronics with new architectures and new materials (e.g., SiC). Just like the junctionless FET biased below the flat-band, the JFET operates in depletion and the current flows in the volume, not at an interface. However, unlike the junctionless FET, the JFET has no gate-insulator layer i.e., there is no semiconductor-insulator interface. This could result in low-frequency noise, which mainly originates from interface traps, and is a clear advantage. Similarly, surface-roughness scattering [183], which degrades mobility, is alleviated to a great extent.

Despite the long use of JFETs in discrete electronics, physics-based compact models today still adopt a conservative approach and deal with the so-called fulldepletion approximation where the deep-depletion regime is essentially modeled empirically. Today, FET compact models [183–186] use regional approximations bridged with smoothing functions. For instance, Sansen and Das [184] adopted a MOSFET-like approach to interpolate the subthreshold, quadratic, and linear modes of operation. Semiempirical log-exponential functions have also been introduced to ensure a smooth transition across the pinch-off domain [184], a technique also used in [187, 188].

This chapter discusses a unified charge-based model for double-gate JFETs addressing fundamental DC, AC, and noise characteristics. The central element considers the JFET as a junctionless FET with a negligible insulating layer i.e., a junctionless FET with an infinite gate capacitance. As for the double-gate junctionless FET, the physics-based model for the JFET will cover all regions of operation, with the exception of accumulation, which is not compatible with the device architecture (forward-biasing of the gate-to-channel pn junctions).

Principle Operation of the JFET

Like the junctionless FET, the JFET has no source and drain pn junction and the channel consists of a highly doped semiconductor layer. However, a major difference exists between these two devices: whereas the junctionless FET has an insulating layer between the channel and the gate electrode(s), in JFETs this role is played by a reversed biased gate-to-channel pn junction i.e., the gate is highly doped to avoid depletion into the gate.

In addition to analytical DC models of junctionless FETs, the design of analog and digital circuits requires accurate modeling of AC characteristics as well. Adopting the charge–voltage relationships presented in Chapter 3, a complete analytical model for transcapacitances valid in all regions of operation is derived for double-gate and nanowire junctionless FETs here.

The charge-based model presented in Chapter 3 covers depletion and accumulation modes. However, at flat-band the derivative of the charge densities with respect to the potential equals, exceeding the theoretical value (but continuity of the charge and derivatives is still preserved). This mismatch around the flat-band prevents obtaining accurate derivatives of the mobile charge density with respect to the applied voltages. In addition, as soon as is increased, the nonuniformity of the channel must also be taken into account to evaluate the equivalent charge densities on the different nodes. Here, a detailed treatment of the charges distribution and partitioning scheme inside the channel of junctionless FETs is given and used to derive a complete small signal-equivalent circuit.

Transcapacitance Matrix in Symmetric Double-Gate FETs

A general analysis of transadmittances is reviewed for symmetric double-gate fieldeffect transistors (see Figure 8.1), no matter the principle of operation (inversion, accumulation, and depletion). The inherent symmetry and the lack of a bulk reference for these architectures results in some unique properties of the matrix transadmittance.

In a harmonic analysis, small-signal current and voltages and are linearly dependent through the so-called Y-matrix transadmittance:

This Y-matrix can be split into two parts: a real number contribution dealing with conductances (matrix conductance) for the in-phase response of the signal and an imaginary number contribution dealing with capacitances for the out-phase contribution (capacitance matrix) (j denotes the imaginary unit and the angular frequency). For a typical MOSFET device with four terminals, gate (g), drain (d), source (s), and body (b), the and matrices have the following elements:

where the element represents the in-phase current response at node i upon a (small) voltage change at node j, which is a transconductance.