The academic literature on silicon photonics is sufficiently rich that one might legitimately ask whether another book in this field is needed. Certainly all of the basic physics of waveguides, modulators, lasers, and photodetectors is covered in great detail in a series of landmark texts, from Yariv and Yeh [1] to Sze and Ng [2] to Siegman [3] and Snyder and Love [4]. More specifically integrated photonics theory is covered comprehensively in texts by Hunsberger [5], Coldren et al. [6], Kaminow et al. [7], etc. Several excellent volumes have come out in recent years describing the state of the field in silicon photonics, and discussing design considerations for a variety of devices [8–15].

So what are we aiming to add to this body of literature? Our aim is not to replicate any of the existing texts' approach, but instead to provide a practical, examples-driven introduction to the practice of designing practical devices and systems. Our (admittedly ambitious) goal for this text is to do something similar to what Mead and Conway did with their landmark text on VLSI [16]: to treat the minimal possible level of device physics, and to focus primarily on the practical design considerations associated with using state-of-the-art silicon photonic foundry processes to build real, useful systems-on-chip.

In order to do this, we focus on a series of tutorials, using the tools that are in use in our own labs. That doesn't mean that these tools are perfect, or that they are necessarily the best tools for any given application: they are just what we have used. Wherever there are alternative approaches, we highlight them and provide some context for why we choose to do things in a certain way. This is obviously an area where errors of omission are very easy to make: we welcome feedback and input.

The vendors of the commercial software we use provide in-kind access for educational institutions. For example, Lumerical Solutions software is available via the Commitment to University Education (CUE) program [17], which provides access to students in undergraduate and graduate classes.

In this chapter, we discuss the impact of manufacturing variability of silicon photonic integrated circuits. The dominant variations in silicon photonics are silicon thickness and feature size. These variations appear from wafer to wafer, as well as within a single photonic integrated circuit. Smoothing due to lithography is also important to consider. Methods of including these variations in the design process are discussed. Finally, some experimental results from on-chip test structures are presented to illustrate the manufacturability and non-uniformity challenge of silicon photonics.

Fabrication non-uniformity

Photonic integrated circuits (PICs) often require precise matching of the central wavelength and the waveguide propagation constants between components on a chip (e.g. ring modulators, optical filters), particularly for wavelength division multiplexing. Understanding the fabrication variability is critical to developing strategies (e.g. thermal tuning) for system implementation, and for determining the cost implications for such compensation strategies (e.g. power consumption).

There have been several studies on the fabrication non-uniformity including intradevice uniformity (e.g. CROWs [1]), within-wafer, wafer-to-wafer, and batch-to-batch variations [2–5]. The dominant fabrication parameter that results in device variation has been identified to be the silicon thickness variation, followed by lithography (e.g. waveguide width) variations.

Zortman et al. [2] found that the thickness variation across 10 cm led to ± 1000 GHz variation in TE resonator wavelength, whereas the width variation contributed to ± 200 GHz. From measurements of TE and TM resonators, they extracted the dimensional variations to be ±5 nm in both thickness and waveguide width (or diameter). The reader is also referred to References [3, 5]. In [5], TE-polarization Bragg gratings, using both strip and rib waveguides, were used to extract thickness variations of approximately ±5 nm, which led to resonance shifts up to 10 nm; these results are consistent with Reference [2].

An example of fabrication non-uniformity, and its impact on device performance, is shown in Figure 11.1. The devices are Bragg gratings, with lengths ranging from 325 µm to 4.9 mm.

We are on the cusp of revolutionary changes in communication and microsystems technology through the marriage of photonics and electronics on a single platform. By marrying large-scale photonic integration with large-scale electronic integration, wholly new types of systems-on-chip will emerge over the next few years.

Electronic-photonic circuits will play a ubiquitous role globally, impacting such areas as high-speed communications for mobile devices (smartphones, tablets), optical communications within computers and within data centres, sensor systems, and medical applications. In particular, we can expect the earliest impacts to emerge in telecommunications, data centers and high-performance computing, with the technology eventually migrating into higher-volume, shorter-reach consumer applications.

In the emerging field of electronics in the 1970s, Lynn Conway at Xerox PARC and Professor Carver Mead at Caltech developed an electronics design methodology, wrote a textbook, taught students how to design electronic integrated circuits, and had their designs fabricated by Intel and HP as multi-project wafers, where several different designs were shared in a single manufacturing run [1]. These efforts led to the foundation of an organization named MOSIS in 1981 that introduced cost sharing of fabrication runs with public access. The inexpensive design-build-test cycle enabled by MOSIS trained, and continues to train, thousands of designers who are responsible for the ubiquity of electronics we see today. MOSIS got started based on commercial processes that were already in production, and opened them up to the design community for prototyping and research purposes.

One of the keys to the long-term success of the microelectronics community, and in particular of the CMOS community, has been this type of access. By making these volume production processes publicly available for research and development at modest cost, anyone with a very modest level of funding is able to do cutting edge, creative work in a process that can instantly go into large-scale production. Training student engineers to use the production tools and processes, and then letting them loose to build cutting-edge circuits which can, with modest funding, be translated into fabless IC start-ups, has been the source of countless successful companies.

In this chapter, we describe the design of these two types of optical input/output coupling techniques: fibre grating couplers in Section 5.2, and edge couplers in Section 5.3. A method of creating a mask layout for a focusing grating coupler is presented. Methods for polarization management are also discussed in Section 5.4.

The challenge of optical coupling to silicon photonic chips

Owing to the large refractive index contrast between the silicon core (n = 3.47 at 1550 nm) and the silicon dioxide cladding (n = 1.444 at 1550 nm), propagation modes are highly confined within the waveguide with dimensions on the order of a few hundred nanometers (see Sections 3.1 and 3.2). Although a benefit for large-scale integration, the small feature size of the waveguide raises the problem of a huge mismatch between the optical mode within an optical fibre and the mode within the waveguide. The cross-sectional area of an optical fibre core (with a diameter of 9°m) is almost 600 times larger than that of a silicon waveguide (with dimensions of 500 nm × 220 nm), hence requires components that adjust the mode-field diameter accordingly.

Several approaches have been demonstrated to tackle the problem of the aforementioned mode mismatch. Edge coupling using spot-size converters and lensed fibres is one solution used to address this, and high-efficiency coupling with an insertion loss below 0.5 dB has been demonstrated [1]. In addition, both TE and TM polarizations can be efficiently coupled. However, this approach can only be used at the edge of the chips, and the implementation of such designs requires complicated post-processes and high-resolution optical alignment, which increase the packaging cost.

Grating couplers are an alternative solution to tackle the issue of mode mismatch. Compared to the edge coupling, grating couplers have several advantages: alignment to grating couplers during measurement is much easier than alignment to edge couplers; the fabrication of grating couplers does not require post-processing, which reduces the fabrication cost; grating couplers can be put anywhere on a chip, which provides flexibility in the design as well as enabling wafer-scale automated testing.