5 - Optical I/O

Summary

In this chapter, we describe the design of these two types of optical input/output coupling techniques: fibre grating couplers in Section 5.2, and edge couplers in Section 5.3. A method of creating a mask layout for a focusing grating coupler is presented. Methods for polarization management are also discussed in Section 5.4.

The challenge of optical coupling to silicon photonic chips

Owing to the large refractive index contrast between the silicon core (n = 3.47 at 1550 nm) and the silicon dioxide cladding (n = 1.444 at 1550 nm), propagation modes are highly confined within the waveguide with dimensions on the order of a few hundred nanometers (see Sections 3.1 and 3.2). Although a benefit for large-scale integration, the small feature size of the waveguide raises the problem of a huge mismatch between the optical mode within an optical fibre and the mode within the waveguide. The cross-sectional area of an optical fibre core (with a diameter of 9°m) is almost 600 times larger than that of a silicon waveguide (with dimensions of 500 nm × 220 nm), hence requires components that adjust the mode-field diameter accordingly.

Several approaches have been demonstrated to tackle the problem of the aforementioned mode mismatch. Edge coupling using spot-size converters and lensed fibres is one solution used to address this, and high-efficiency coupling with an insertion loss below 0.5 dB has been demonstrated [1]. In addition, both TE and TM polarizations can be efficiently coupled. However, this approach can only be used at the edge of the chips, and the implementation of such designs requires complicated post-processes and high-resolution optical alignment, which increase the packaging cost.

Grating couplers are an alternative solution to tackle the issue of mode mismatch. Compared to the edge coupling, grating couplers have several advantages: alignment to grating couplers during measurement is much easier than alignment to edge couplers; the fabrication of grating couplers does not require post-processing, which reduces the fabrication cost; grating couplers can be put anywhere on a chip, which provides flexibility in the design as well as enabling wafer-scale automated testing.