Chapter 7 deals with fully-depleted SOI and double-gate MOSFETs. A general, asymmetric double-gate model is applied to long channel SOI MOSFETs. For symmetric double-gate MOSFETs – the generic form of FinFETs, an analytic potential model is described that covers all regions of operation continuously. The scale length model first introduced in Chapter 6 for bulk MOSFETs is modified for short-channel DG MOSFETs. Nanowire MOSFET models, both long and short channel, are also discussed. The last section examines the scaling limits of DG and nanowire MOSFETs based on quantum mechanical considerations.

This chapter begins by reviewing MOSFET scaling – the guiding principle for achieving density, speed, and power improvements in VLSI evolution. The implications of the non-scaling factors, specifically, thermal voltage and silicon bandgap, on the path of CMOS evolution are discussed. The rest of the chapter deals with the key factors that govern the switching performance and power dissipation of basic digital CMOS circuits. After a brief description of static CMOS logic gates, their layout, and noise margin, Section 8.3 considers the parasitic resistances and capacitances that may adversely affect the delay of a CMOS circuit. These include source and drain series resistance, junction capacitance, overlap capacitance, gate resistance, and interconnect capacitance and resistance. In Section 8.4, a delay equation is formulated and applied to study the sensitivity of CMOS delay to a variety of device and circuit parameters such as wire loading, device width and length, gate oxide thickness, power-supply voltage, threshold voltage, parasitic components, and substrate sensitivity in stacked circuits. The last section addresses the performance factors of MOSFETs in RF circuits, in particular, the unity-current-gain frequency and unity-power-gain frequency.

Chapter 2 covers the appropriate level of basic device physics to make the book self-contained, and to prepare the reader with the necessary background on device operation and material physics to follow the discussion in the rest of the book. Starting with the energy bands in silicon, Chapter 2 introduces the basic concepts of Fermi level, carrier concentration, drift and diffusion current transport, and Poisson’s equation. Also addressed in this chapter are generation and recombination, minority carrier lifetime, and current continuity equation.

Chapter 10 covers the basic design of a bipolar transistor. The design of the individual device regions, namely the emitter, the base, and the collector, are discussed separately. Since the detailed characteristics of a bipolar transistor depend on its operating point, the focus of this chapter is on optimizing the device design according to its intended operating condition and environment, and on the tradeoffs that must be made in the optimization process. The physics and characteristics of SiGe-base bipolar transistors are discussed in depth. The design of symmetric lateral bipolar transistors on SOI is also covered, including the development of analytical models for the device parameters, base and collector currents, and the transit times.

Chapter 5 describes the basic characteristics of MOSFET devices, using n-channel MOSFET as an example for most of the discussions. It deals with the more elementary long-channel MOSFETs, with sections on the charge sheet model, regional I–V models, and subthreshold current characteristics. A recently developed non-GCA model gives insights to the saturation region behavior while clarifying the misleading term of “pinch-off” in most standard textbooks. In the section on channel mobility, the strain effects, both biaxial and uniaxial, on electron and hole mobilities are discussed. The last section addresses the body effect, temperature effect, and quantum effect on the long-channel threshold voltage.

In Chapter 12, the basic operational and device design principles of commonly used memory devices are discussed. The memory devices covered include CMOS SRAM, DRAM, bipolar SRAM, and several commonly used in nonvolatile memories. Typical read, write, and erase operations of the various memory arrays are explained. The issue of noise margin in scaled CMOS SRAM cells is discussed. A brief discussion of more recent developments of NAND flash technologies, including multi-bit per cell, 3D NAND, and wear leveling is given.

The basic components of a bipolar transistor are described in Chapter 9. Both vertical bipolar transistors, including SiGe-base transistors, and symmetric lateral bipolar transistors on SOI are covered. The discussion focuses on the vertical n–p–n transistors, since they are the most commonly used. The difference between n–p–n vertical transistors and symmetric lateral n–p–n transistors are pointed out where appropriate. The basic operation of a bipolar transistor is described in terms of two p–n diodes connected back to back. The basic theory of a p–n diode is modified and applied to derive the current equations for a bipolar transistor. From these current equations, other important device parameters and phenomena, such as current gain, Early voltage, base widening, and diffusion capacitance, are examined. The basic equivalent-circuit models relating the device parameters to circuit parameters are developed. These equivalent-circuit models form the starting point for discussing the performance of a bipolar transistor in circuit applications.