Too often there is thought to be a dichotomy between science and engineering: science as a quest for knowledge and understanding, and engineering as the art of constructing useful objects. This book, based on the author's experience in leading a silicon compilation project at Philips Research, is exceptional in that it very convincingly demonstrates the effectiveness of combining the scientific method with sound engineering practices.

Aimed at bridging the gap between program construction and VLSI design, the research reported in this book extends over an unusually wide spectrum of disciplines, ranging from computer science and electrical engineering to logic and mathematics. In this exciting arena we encounter such topics as the power dissipation of an assignment statement, the mathematical theory of handshake circuits, the correctness proof of a compiler, and the problem of circuit initialization without reset wires, to mention just a few.

Such a multi-faceted study can be successful only if it is able to demonstrate a clear separation of concerns. In this respect, Kees van Berkel does an admirable job: his concept of handshake circuits provides an extremely elegant interface between algorithm design on the one hand and circuit implementations on the other. This separation between ‘what’ and ‘how’, which many researchers and practitioners find difficult to apply, turns out to be amazingly fruitful, as the readers of this book are encouraged to discover for themselves. In my opinion we are, with the publication of this book, witnessing a major step forward in the development of the discipline of VLSI programming.

This book is about the design of digital VLSI circuits. Whereas LSI circuits perform basic functions such as multiplication, control, storage, and digital-to-analog conversion, VLSI circuits contain complex compositions of these basic functions. In many cases all data and signal processing in a professional or consumer system can be integrated on a few square centimeters of silicon. Examples of such “systems on silicon” can be found in:

• Disc (CD) players,

• Disc Interactive (CDI) players,

• Compact Cassette (DCC) players,

• Audio Broadcast (DAB) receivers,

• radios and mobile telephones,

• High-Definition TeleVision (HDTV) sets,

• video recorders,

• processors,

• car-navigation systems,

• processors, and

• test and measurement systems.

These systems generally process analog as well as digital signals, but the digital circuits dominate the surface of an IC. The memory needed for storing intermediate results often covers a significant fraction of the silicon area.

Systems on silicon are tending to become more complex and are tending to increase in number. The increase in complexity follows from advances in VLSI technology, and the rapid growth of the number of transistors integrated on a single IC. The constant reduction of the costs of integration makes integration economically attractive for an increasing number of systems. Also, the rapid succession of generations of a single product increases the pressure on design time. The ability to integrate systems on silicon effectively, efficiently, and quickly has thus become a key factor in the global competition in both consumer and professional electronic products.

This book pursues a programming approach to the design of digital VLSI circuits. In such an approach the VLSI-system designer constructs a program in a suitable high-level programming language. When he is satisfied with his program, the designer invokes a so-called silicon compiler which translates this program into a VLSI-circuit layout.

The choice of the programming language is a crucial one, for it largely determines the application area, the convenience of design, and the efficiency of the compiled circuits. A good VLSI-programming language.

1. 0. is general purpose in that it allows the description of all digital functions;

2. 1. encourages the systematic and efficient design of programs by abstracting from circuit, geometry and technology details;

3. 2. is suitable for automatic translation into efficient VLSI circuits and test patterns.

Below follows a motivation for these requirements.

1. 0. A wide range of applications is required to justify the investment in tools and training.

2. 1. A major gain in design productivity can be expected by designing in a powerful highlevel language. Furthermore, system designers do not need to resort to VLSI specialists. Systematic design methods, supported by mathematical reasoning, are required to deal with the overwhelming complexity involved in the design of VLSI systems.

3. 2. Automatic translation to VLSI circuits avoids the introduction of errors at the lower abstraction levels. It also becomes attractive to design alternative programs and compare the translated circuits in costs (circuit area) and performance (speed and power).

Overview

Aims

This chapter describes a set of preliminary layout experiments using the system of three-dimensional abutment just described. The experiments are designed to configure the system and prepare the way for the experiments described in the next chapter. Specifically, the following questions are addressed:

• What are the important components of the merit functions?

• How should the components of the merit functions be weighted?

• What are the best algorithm control strategies?

• Is the system behaving sensibly?

The system is deliberately designed to operate in a highly flexible manner, and a primary goal of this first set of experiments is to determine those settings of the system parameters which produce the best layouts according to metrics which are discussed. This involves the postulation and evaluation of merit function components to control both placement and routing. In addition, the effect of different algorithm control strategies on layout is investigated, particularly the effect of the cluster shape and routing space controls. Finally, the system is used on circuits which are known to have optimal embeddings in the three-dimensional framework, and the results are used to indicate that the system exhibits appropriate behaviour and that the chosen system parameters are suitable.

Methods

The general experimental method used to determine the effect of some parameter or algorithm control is now described. First, a set of circuits for which layouts are constructed is defined. A variety of mainly random logic circuits is chosen in order to measure the layout system behaviour for a range of circuits. Each circuit is described in terms of simple NAND gates.

The configuration file of the Qudos Layout Editor describes routable layers such as metal and polysilicon and via layers which describe the relationship between routable layers. For three-dimensional CMOS SOI design rules, a vertical connection is described by a metal layer with no contact overlap. The contact overlap will be provided on the planar metal layer to which the vertical metal layer connects. The structure of the layers is shown in Figure A.1. The layer ‘Dummy’ avoids a limitation of the system, and is introduced to maintain full design rule checking. The corresponding configuration file is included below.

Wiring schemes

Introduction

A number of limitations imposed by the technology of three-dimensional integration have been mentioned. These limitations restrict the total number of transistors and the number of layers in which transistors can be constructed. However, for a given number of layers the topology of circuit layout is most profoundly affected by the availability and quality of wiring both within and between the layers.

For the layout problem, the distribution of wiring is determined by the edges in the physical layout graph, which is the initially empty spatial grid in which edges are wires and vertices are transistors or gates. The logical circuit graph specifies the structural connectivity of the circuit in terms of nodes and signals. Since layout consists of embedding the logical circuit graph into the physical layout graph, the pattern of edges in the physical graph has an effect on the compactness of the embedding. Contact and wiring techniques are now discussed.

Contact techniques

A range of contact techniques are available for three-dimensional structures, providing direct connection between diffusion, gate and wiring regions. Conventional contact methods which are used for connections within a single layer of transistors can be applied to create direct connections between layers of transistors. With the butting contact, regions are connected by contact with the wiring material which is particularly useful when the signal connected is required elsewhere in the circuit. In particular, connection can be formed between the gate and diffusion regions of a single transistor (Figure 4.1(a)), or a pair of stacked transistors (Figure 4.1(b)) [Kawamura 83].

Review

Aims

This dissertation has presented an investigation into three-dimensional integrated circuit layout and cell design. The primary goal of the investigation was to discover the potential benefits of such layout, and to determine whether those benefits justify the considerably more complex and costly techniques of fabrication which are involved.

Similar questions for other difficult fabrication techniques are more readily answered. The cost of techniques used to make smaller transistors is constantly being justified by the denser, faster and more highly integrated circuits and systems which result. It is also the case that such technology does not introduce any fundamentally new layout problems. A more difficult question to answer concerns the value of wafer-scale integration. This is because the benefits are clouded by yield problems, and new layout and fabrication methodologies must be introduced to achieve fault or failure tolerance. The best methods are still to be determined.

The value of three-dimensional integration is a yet more difficult question. The technological difficulties are as apparent as they are abundant, and include yield degradation and thermal stresses during fabrication and heat dissipation and crosstalk during circuit operation. However, the nature of the benefit is not clear. It has been speculated that three-dimensional circuits might be denser and faster, having shorter wiring and offering greater connection capabilities. These benefits are expected because of the inherently richer connection topology which the three-dimensional arrangement of devices offers. Little has been done and less has been published about such speculation.

Preliminary research

As with any new topic of such complexity, an investigation into three-dimensional integrated circuit layout is open-ended.

Layout by abutment

Introduction

The previous two chapters have outlined the technology enabling three-dimensional circuits to be constructed, and have examined some topologies which might result from the application of such technology. Some of the potential benefits of three-dimensional integration have been mentioned. These benefits are expected largely as a result of reduced wire length and device separation, and of the inherently richer connection topologies of three-dimensional circuits as shown in the two- and three-dimensional layouts of a half-adder circuit. The work by Leighton and Rosenberg on layout within a three-dimensional grid does not present a particularly optimistic view of three-dimensional circuits. This is primarily because of the restrictive assumptions in the adopted layout model which are necessary for the method of analysis employed.

It is the aim of this chapter to introduce a method of performing three-dimensional layout which will be the vehicle for a range of experiments. The method involves the postulation of a library of three-dimensional cells with particular geometric properties and the layout of circuits by combining the cells in a novel manner. It will be shown how the method can be used to perform layout in a number of ways, with a range of connection topologies. The chapter concludes with the physical design of logic cells which could form the basis of a practical system. Dimensions extracted from these cell designs will be used to scale the results of the layout experiments described in the next chapter.

Smaller wiring spaces

For two-dimensional integrated circuits, enhanced process capabilities can result in reduced feature sizes leading to smaller transistors and thinner wires.

Introduction

Aims

The previous chapter presented a preliminary set of experiments which were designed to examine the performance of different operating configurations of the layout system. The experiments were confined to a single three-dimensional layout environment based on a fixed number of layers of cuboid cells with one connection per face. This chapter describes a second set of experiments which build on the above findings and which explicitly investigate the properties of three-dimensional layouts. The questions addressed are:

• How does cell library design affect layout?

• How does the separation between layers of cells affect layout?

• How many layers of cells offer improvement?

• How do the results compare with two-dimensional layout?

In the first experiment, a comparison is made between layouts using different libraries of cells. The cell design exercise presented in chapter five is revisited and the design of more complex cells with greater active connection capability is presented. The dimensions of these cells are used to make absolute comparisons between layouts using different libraries of cells. The second experiment investigates a technological advantage of three-dimensional integration which is the potentially small separation between device layers. The effect of reduced vertical separation on the quality of layout is examined.

A key question about three-dimensional layout concerns the benefit of using more layers of active cells. This is the subject of the third experiment, which includes an examination of how the layout system behaves with a single active layer, and how additional wiring layers are utilised.

Thesis aims

A study of three-dimensional integrated circuit layout is presented in this dissertation. Three-dimensional integrated circuits are those in which active devices such as transistors are fabricated in each of at least two vertically stacked semiconducting planes. An evaluation of the potential benefits of using three-dimensional integration is carried out. Such benefits include greater layout densities, shorter interconnection lengths and faster circuits. Emphasis is placed on considering the layout methods required to use three-dimensional fabrication techniques and to accrue the above benefits.

Three-dimensional circuits are one of a number of recent developments in integrated circuit construction techniques to have stimulated interest. Other developments include the use of a variety of semiconductor and wiring materials for faster transistors and connections, and enhanced processing techniques to improve yield and reduce transistor geometries. This enables both physically larger and logically more complex circuits to be integrated. These developments do not present any new layout problems. The search for better, more automated layout continues independently of such technological advances. The same is not true in the three-dimensional domain. The juxtaposition of devices in three dimensions presents an inherently different set of connection properties to the two-dimensional case, since a device may now have neighbours above and below in addition to those in the semiconducting plane. Layout in three dimensions requires new techniques to fully exploit this property.

Since three-dimensional fabrication techniques were first demonstrated in the early eighties [Gibbons 80], two areas of research have been explored. The primary research has concentrated on the necessary fabrication techniques.

Some recent developments in semiconductor process technology have made possible the construction of three-dimensional integrated circuits. Unlike other technological developments in two-dimensional integration, these circuits present a new and inherently richer connection topology. This offers the potential for improved layout in terms of increased density and reduced interconnect length. These circuits will be difficult and expensive to manufacture, at least in the short term, and the scale of the improvement in layout is not apparent. This dissertation presents a discussion of layout and design for three-dimensional integrated circuits.

A number of materials and techniques can be used in the manufacture of such circuits. This choice has a profound bearing on the topology of circuit layout. A classification relating process technology to layout topology is developed and illustrated with the design of a number of circuits. A layout system is presented as the vehicle for a series of experiments in three-dimensional layout. It is shown that the system can be constrained to perform circuit layout in a number of topologies in the classification.

Finally, some attempt to quantify the benefits of three-dimensional layout is made. The layout model is calibrated by designing examples of basic circuit elements.

I am indebted to my supervisor, Andy Hopper, for his encouragement and support. He first introduced me to the topic of computer aided design of integrated circuits when I was an undergraduate, and has been a source of guidance ever since. I am also indebted to Roger Needham for extending the facilities of the Computer Laboratory. I am grateful that both Andy and Roger have demonstrated quite remarkable patience. The Science and Engineering Research Council provided funding for three years for which I am thankful.

Of the many people who have been a source of help, I would particularly like to thank David Wheeler for a number of stimulating discussions, and Haroon Ahmed of the Microcircuit Engineering Laboratory for introducing me to the technology of three-dimensional circuits. Alan Mathewson and Ciaran Cahill, of the National Microelectronics Research Centre, University College, Cork, have contributed to my further understanding of the technological possibilities. Elements of the systems used in the case study described in chapter two were developed by myself, Jeremy Dion, Alan Jones, Tony Mann, Trevor Morris, John Porter, Peter Robinson and Chris Stenton. I would like to thank Tony Mann and John Porter for reminding me about the details of the placement and routing schemes.

Chris Stenton and Steve Temple have contributed many helpful suggestions particularly in the experimental stages and were diligent proof readers, as were Tim Cole and David Greaves. I am grateful for their suggestions for improvements.