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Published online by Cambridge University Press: 05 May 2010
The configuration file of the Qudos Layout Editor describes routable layers such as metal and polysilicon and via layers which describe the relationship between routable layers. For three-dimensional CMOS SOI design rules, a vertical connection is described by a metal layer with no contact overlap. The contact overlap will be provided on the planar metal layer to which the vertical metal layer connects. The structure of the layers is shown in Figure A.1. The layer ‘Dummy’ avoids a limitation of the system, and is introduced to maintain full design rule checking. The corresponding configuration file is included below.
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