2 - Transaction-level system modeling

Summary

Model-based verification has been the bedrock of electronic design automation. Over the past several years, system modeling has evolved to keep up with improvements in process technology fueled by Moore's law. Modeling has also evolved to keep up with the complexity of applications resulting in various levels of abstraction. The design automation industry has evolved from transistor-level modeling to gate level and eventually to register-transfer level (RTL). These models have been used for simulation-based verification, formal verification, and semi-formal verification.

With the advent of embedded systems, the software content in most modern designs is growing rapidly. The increasing software content, along with the size, complexity, and heterogeneity of modern systems, makes RTL simulation extremely slow for any reasonably sized system. This has made system verification the most serious obstacle to time to market.

The root of the problem is the signal-based communication modeling in RTL. In any large design there are hundreds of signals that change their values frequently during the execution of the RTL model. Every signal toggle causes the simulator to stop and re-evaluate the state of the system. Therefore, RTL simulation becomes painfully slow. To overcome this problem, designers are increasingly resorting to modeling such complex systems at higher levels of abstraction than RTL.

In this chapter, we present transaction-level models (TLMs) of embedded systems that replace the traditional signal toggling model of system communication with function calls, thereby increasing simulation speed. We discuss essential issues in TLM definition and explore different classifications as well as cases for TLMs. We will also provide an understanding of the basic building blocks of TLMs.