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7 - Nanowire Transistor Circuits

Published online by Cambridge University Press:  05 April 2016

Jean-Pierre Colinge  and
James C. Greer
Jean-Pierre Colinge
Affiliation:
Taiwan Semiconductor Manufacturing Company Limited (TSMC)
James C. Greer
Affiliation:
Tyndall National Institute, Ireland
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Summary

CMOS circuits

Nanowire FETs can be used in the same fashion as any other type of MOSFET to construct the logic gates that are the building blocks for data processors and control circuits, as well as memory cells of various types such as static random access memory (SRAM), flash memory, and so on. The topology of nanowire transistors makes them particularly suitable for making array-like circuits such as crossbar nanowire circuits and nanoscale application-specific integrated circuits. Nanowire FETs can even be used as photodetectors [1]. Last but not least, nanowire transistor-based sensors can also be combined with CMOS electronics to deliver powerful chemical or biomedical analytical devices.

Nanowire transistors can be used as single devices. They can also be used in serial or parallel combinations. Figure 7.1 shows horizontal nanowire transistors in a parallel configuration; using this architecture a high current drive with a small layout footprint can be achieved [2]. Vertical nanowire transistors lend themselves quite naturally to the formation of NAND-based architectures as shown in Fig. 7.2.

CMOS logic

Techniques for the design and optimization of nanowire circuits are still in their infancy. Key performance indicators (KPIs) include ON/OFF currents, effective current and effective gate capacitance, CV/I, integration density, and other performance measures normally associated with CMOS transistors. Key process and layout parameters include number of nanowires per transistor, footprint, nanowire diameter, and other process-related parameters such as gate length, gate over-underlap length and source/drain (S/D) region length. One particular study indicates that through design optimization, the total capacitance and parasitic resistance of typical nanowire CMOS gates can be reduced by over 80% compared to nanowire designs without optimized process parameters. Significant improvements are achieved through the reduction of the source/drain extension length, gate overlap, and nanowire diameter. Optimization of the device parameters can also achieve an improvement of over 90% reduction in delay and power consumption at the circuit level [3].

With the decrease of both device dimensions and supply voltage, variability has become an important issue in integrated circuit fabrication. Device parameters such as threshold voltage, drain-induced barrier lowering (DIBL), and ON and OFF currents exhibit statistical variations. The origins of these variations are multiple and include gate line edge roughness (LER), random doping fluctuations (RDF), nanowire diameter variations, and/or nanowire surface roughness.

Type
Chapter
Information
Nanowire Transistors
Physics of Devices and Materials in One Dimension
 , pp. 221 - 248
Publisher: Cambridge University Press
Print publication year: 2016

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