High-Electron Mobility Transistors (HEMTs) can be prepared by growing alternating epitaxial layers of InAlAs and InGaAs on InP substrates. Lattice matched HEMTs are obtained by growing layers of InxAl(1-x)As and InyGa(1-y)As with x ≃ 0.5227 and y ≃ 0.5324. Varying the values of x and y by controlling the individual flux during molecular-beam epitaxial (MBE) growth, one can obtain pseudomorphic HEMTs. Pseudomorphic HEMTs may have superior electronic transport properties and larger conduction band discontinuity when compared to an unstrained one. The precise control of the composition is thus important to the properties of HEMTs. This control is however very difficult and the values of x and y may vary from run to run.

We will demonstrate in this paper the capability of a double crystal rocking curve (DCRC) on the structure characterization. All the structure information: including composition and thickness of both the buffer and top InAlAs layers and the active channel InGaAs layer, can be obtained from one x-ray diffraction measurement. It is accomplished through a computer simulation process of DCRCs. The structure parameters of the epitaxial layers are used to calculate (simulate) the DCRCs. The simulated one is then to compare with the experimental curves. During the simulation one or more of these structure parameters are adjusted until the best fitted DCRC is obtained. The limitation of DCRC in measuring small variations in layer thickness as well as the small changes in composition for both InAlAs and InGaAs layers will be discussed.

Formation and characterization of a new hetero -structure of modulation doped p-Si0.5Ge0.5/Ge/Si1-xGex are comprehensively studied. In the MBE growth, thick Si1-xGex buffer layers are grown incommensurately at high temperature (520°C), and thin Si0.5Ge0.5/Ge layers are grown commensurately at low temperature (≦450°C). The strain field in the Ge channel layers can be precisely controlled by changing the Si composition (1-X) in the Si 1 -xGex buffer layers. As a result, a large energy discontinuity in the valence band (0.17 eV) is realized at the hetero -interface of p-Si0.5Ge0.5/Ge. This enables a high mobility of two -dimensional hole gas (4500 cm2/Vs) at 77 K.

Anisotropic electron transport has been observed in InxGa1-xAs/GaAs heterostructures grown by MOVPE on (001) and intentionally misoriented GaAs substrates. The low field electron mobilities in two perpendicular directions are found to be higher in the [110] direction than in the [110] direction. The ratio of µ[110]/µ[110] derived from Hall measurements is related to the degree of substrate misorientation as well as epilayer composition. Finally, the photoluminescence spectra are polarized along orthogonal <110> directions. These anisotropic properties are directly related to the anisotropy of [110] and [110] dislocations due to lattice mismatch between the substrates and the layers.

Structural and electrical characteristics of the GaAs1-xPx / GaAs and GaAs/GaAs1-xPx/GaAs (x=0.02, 0.05, 0.08, 0.16 and 0.32) hetero-epitaxial systems have been investigated using X-ray rocking curve technique, Optical Beam Induced Current imaging, Nomarski Micrograph, and I-V-T and C-V measurements. The rocking curve Full Width Half Maximum of the GaAs1-xPx epilayer increased sharply at x=0.16 due to a decreased layer thickness and increased in-plane mismatch. The cross-hatched line density in the OBIC image and Nomarski Micrograph increases as the lattice mismatch increases. The epilayer surface morphology is dependent on the layer thickness. The forward I-V characteristics of Au-GaAsP/GaAs and Au-GaAs/GaAsP/GaAs Schottky diodes showed an increased tunneling current for an the increased lattice mismatch. For GaAsP/GaAs structure with a higher phosphorus composition, Fermi-level pinning caused by misfit dislocation was observed. Au-GaAs/GaAsP/GaAs Schottky diodes show an excess current at the low temperature, high field range which, we believe, is due to defect related tunneling.

Different in-plane mismatch was introduced by varying the Ga 0.92In0.08As(p+) epilayer thickness (h-0.1, 0.25, 0.5 and lum) on GaAs(n)/GaAs(n+) structure. For sample with h-lum, quasi-Fermi level pinning effect was observed in low temperature forward Current-Voltage characteristic due to high density misfit dislocation. From Vint measurement at low frequency limit in C-2 vs Voltage plot, interface state density Nss was obtained. From Capacitance-Voltage measurements at different frequencies, single-level interface state density Ns was estimated using Schokley-Read-Hall statistics. Both Nss and Ns show their linear relation with epilayer in-plane mismatch. Admittance Spectroscopy shows an interface trap level at about Ev + 0.36 eV with the hole capture cross section cp = 2.7×10-15 cm-2 for the h-lum sample, and at Ev + 0.21 eV with cP = 2.4×10-16 cm-2 for the h-0.5um sample.

We suggest a new field effect transistor based on strain-induced polarization charges. The structure utilizes the pseudomorphic growth of a strained barrier layer on a substrate oriented in a polar direction such as [111] or [211]. Polarization charges in the barrier layer are generated by the piezoelectric effect. A two-dimensional (2-D) electron gas, whose density can be modulated by an external bias, forms at the hetero-interface and it screens the polarization charge. Zero bias densities of several 1011 e/cm2 and threshold voltages of 0.5 V can be achieved. Both normally-on and normally-off structures are possible.

A new power MISFET with undoped GaAs-Al0.3Ga0.7As superlattice gate “insulator” and buffer structure has been fabricated successfully. The superlattice gate “insulator” exhibits a much higher gate breakdown voltage( >35V) with very low prebreakdown leakage current and a lower gate capacitance (C ). Due to the existence of gate “insulator”, a higher carrier concentration can be employed in the active channel which improves the output drain current capability and transconductance. If the gate length is reduced to 1 um, a higher transconductance up to 330 mS/mm can be expected.

The insertion of superlattice buffer structure, between active channel and buffer layer offers an excellent carrier confinement barrier and gives an interface degraded region smaller than 40A. In addition, the superlattice buffer structure can getter greatly deep level impurities and defects from substrate or buffer layer. In summary, the proposed MISFET structure is suitable for high power, high frequency and low noise applications.

InP field-effect transistors fabricated with an amorphous hydrogenated Si (a-Si:H) gate resulted in metal-insulator-like FET characteristics with no observable current drift and a transconductance of 30–38 mS/mm. The high stability of this gate system is attributed to the low temperature of deposition and the hydrogen passivation of the InP surface.