After reading to this point in the book, you now have the skills to design complex combinational and sequential logic modules. However, if someone were to ask you to design a DVD player, a computer system, or an Internet router you would realize that each of these is not a single finite-state machine (or even a single datapath with associated finite-state controller). Rather, a typical system is a collection of modules, each of which may include several datapaths and finite-state controllers. These systems must first be decomposed into simple modules before the design and analysis skills you have learned in the previous chapters can be applied. However, the problem remains that of how to partition the system to this level where the design becomes manageable. This system-level design is one of the most interesting and challenging aspects of digital systems.

Memory is widely used in digital systems for many different purposes. In a processor, SDDR DRAM chips are used for main memory and SRAM arrays are used to implement caches, translation lookaside buffers, branch prediction tables, and other internal storage. In an Internet router (Figure 23.3(b)), memory is used for packet buffers, for routing tables, to hold per-flow data, and to collect statistics. In a cellphone SoC, memory is used to buffer video and audio streams.

A memory is characterized by three key parameters: its capacity, its latency, and its throughput. Capacity is the amount of data stored, latency is the amount of time taken to access data, and throughput is the number of accesses that can be done in a fixed amount of time.

A memory in a system, e.g., the packet buffer in a router, is often composed of multiple memory primitives: on-chip SRAM arrays or external DRAM chips. The number of primitives needed to realize a memory is governed by its capacity and its throughput. If one primitive does not have sufficient capacity to realize the memory, multiple primitives must be used – with just one primitive accessed at a time. Similarly, if one primitive does not have sufficient bandwidth to provide the required throughput, multiple primitives must be used in parallel – via duplication or interleaving.

In this appendix we present a few guidelines for VHDL coding style. These guidelines grew out of experience with both VHDL and Verilog description languages. These guidelines developed over many years of teaching students digital design and managing design projects in industry, where the guidelines have been proven to reduce effort, to produce better final designs, and to produce designs that are more readable and maintainable. The many examples of VHDL throughout this book serve as examples of this style. The style presented here is intended for synthesizable designs – VHDL design entities that ultimately map to real hardware. A very different style is used in testbenches. This section is not intended to be a reference manual for VHDL. The following appendix provides a brief summary of the VHDL syntax used in this book and many other references are available online. Rather, this section gives a set of principles and style rules that help designers write correct, maintainable code. A reference manual explains what legal VHDL code is. This appendix explains what good VHDL code is. We give examples of good code and bad code, all of which are legal.

Verification and test are engineering processes that complement design. Verification is the task of ensuring that a design meets its specification. On a typical digital systems project, more effort is expended on verification than on the design itself. Because of the high cost and long delays involved in fabricating a chip, thorough verification is essential to ensure that the chip works the first time. A design error that is not caught during verification would result in costly delays and retooling.

Testing is performed to ensure that a particular instantiation of a design functions properly. When a chip is fabricated, some transistors, wires, or contacts may be faulty. A manufacturing test is performed to detect these faults so the device can be repaired or discarded.

The output of sequential logic depends not only on its input, but also on its state, which may reflect the history of the input. We form a sequential logic circuit via feedback – feeding state variables computed by a block of combinational logic back to its input. General sequential logic, with asynchronous feedback, can become complex to design and analyze due to multiple state bits changing at different times. We simplify our design and analysis tasks in this chapter by restricting ourselves to synchronous sequential logic, in which the state variables are held in a register and updated on each rising edge of a clock signal (clk).

The behavior of a synchronous sequential logic circuit, or finite-state machine (FSM), is completely described by two logic functions: one that computes its next state as a function of its input and present state, and one that computes its output – also as a function of its input and present state. We describe these two functions by means of a state table, or graphically with a state diagram. If states are specified symbolically, a state assignment maps the symbolic states onto a set of bit vectors – both binary and one-hot state assignments are commonly used.

Given a state table (or state diagram) and a state assignment, the task of implementing a finite-state machine is a simple one of synthesizing the next-state and output logic functions. For a one-hot state encoding, the synthesis is particularly simple because each state maps to a separate flip-flop and all edges in the state diagram leading to a state map into a logic function on the input of that flip-flop. For binary encodings, Karnaugh maps for each bit of the state vector are written and reduced to logic equations.

Finite-state machines can be implemented in VHDL by creating a state register to hold the current state, and describing the next-state and output functions with combinational logic descriptions, such as case statements as described in Chapter 7. State assignments should be specified using constants to allow them to be changed without altering the machine description itself. Special attention should be given to resetting the FSM to a known state at startup.

In a synchronous system, we can avoid putting our flip-flops in illegal or metastable states by always obeying the setup- and hold-time constraints. When sampling asynchronous signals or crossing between different clock domains, however, we cannot guarantee that these constraints will be met. In these cases, we design a synchronizer that, through a combination of waiting for metastable states to decay and isolation, reduces the probability of synchronization failure.

A brute-force synchronizer consisting of two back-to-back flip-flops is commonly used to synchronize single-bit signals. The first flip-flop samples the asynchronous signal and the second flip-flop isolates the possibly bad output of the first flip-flop until any illegal states are likely to have decayed. Such a brute-force synchronizer cannot be used on multi-bit signals unless they are encoded with a Gray code. If multiple bits are in transition when sampled by the synchronizer, they are independently resolved, possibly resulting in incorrect codes, with some bits sampled before the transition and some after the transition. We can safely synchronize multi-bit signals with a FIFO (first-in first-out) synchronizer. A FIFO serves both to synchronize the signals and to provide flow control, ensuring that each datum produced by a transmitter in one clock domain is sampled exactly once by a receiver in another clock domain – even when the clocks have different frequencies.

In Chapter 10 we introduced the basics of computer arithmetic: adding, subtracting, multiplying, and dividing binary integers. In this chapter we continue our exploration of computer arithmetic by looking at number representation in more detail. Often integers do not suffice for our needs. For example, suppose we wish to represent a pressure that varies between 0 (vacuum) and 0.9 atmospheres with an error of at most 0.001 atmospheres. Integers don't help us much when we need to distinguish 0.899 from 0.9. For this task we will introduce the notion of a binary point (similar to a decimal point) and use fixed-point binary numbers.

In some cases, we need to represent data with a very large dynamic range. For example, suppose we need to represent time intervals ranging from 1 ps (10−12 s) to one century (about 3 × 109 s) with an accuracy of 1%. To span this range with a fixed-point number would require 72 bits. However, if we use a floating-point number – in which we allow the position of the binary point to vary – we can get by with 13 bits: six bits to represent the number and seven bits to encode the position of the binary point.

In Chapter 6 we saw how to synthesize combinational logic circuits manually from a specification. In this chapter we show how to describe combinational circuits in the VHDL hardware description language, building on our discussion of Boolean expressions in VHDL (Section 3.6) and the initial discussion of VHDL (Section 1.5). Once the function has been described in VHDL, it can be automatically synthesized, eliminating the need for manual synthesis.

Because all optimization is done by the synthesizer, the main goal in writing synthesizable VHDL is to make it easily readable and maintainable. For this reason, descriptions that are close to the function of a design (e.g., a truth table specified with a case statement) are preferable to those that are close to the implementation (e.g., equations using a concurrent assignment statement, or a structural description using gates). Descriptions that specify just the function tend to be easier to read and maintain than those that reflect a manual implementation of the function.

To verify that a VHDL design entity is correct, we write a testbench. A testbench is a piece of VHDL code that is used during simulation to instantiate the design entity to be tested, generate input stimulus, and check the design entity's outputs. While design entities must be coded in a strict synthesizable subset of VHDL, testbenches, which are not synthesized, can use the full VHDL language, including looping constructs. In a typical modern digital design project, at least as much effort goes into design verification (writing testbenches) as goes into doing the design itself.

The interconnect between modules is as important a component of most systems as the modules being connected. As described in Section 5.6, wires account for a large fraction of the delay and power in a typical system. A wire of just 3 μm in length has the same capacitance (and hence dissipates the same power) as a minimum-sized inverter. A wire of about 100 μm in length dissipates about the same power as one bit of a fast adder.

Whereas simple systems are connected with direct point-to-point connections between modules, larger and more complex systems are better organized with a bus or a network. Consider an analogy to a telephone or intercom system. If you need to talk to only two or three people, you might use a direct line to each person you need to talk to. However, if you need to talk to hundreds of people, you would use a switching system, allowing you to dial any of your correspondents over a shared interconnect.

In this chapter, we look at three methods for improving the speed of arithmetic circuits, and in particular multipliers. We start in Section 12.1 by revisiting binary adders and see how to reduce their delay from O(n) to O(log(n)) by using hierarchical carry-look-ahead circuits. This technique can be applied directly to build fast adders and is also used to accelerate the summation of partial products in multipliers. In Section 12.2 we see how the number of partial products that need to be summed in a multiplier can be greatly reduced by recoding one of the inputs as a sequence of higher-radix, signed digits. Finally, in Section 12.3 we see how the partial products can be accumulated with O(log(n)) delay by using a tree of full adders. The combination of these three techniques into a fast multiplier is left as Exercises 12.17 to 12.20.

Flip-flops are among the most critical circuits in a modern digital system. As we have seen in previous chapters, flip-flops are central to all synchronous sequential logic. Registers (built from flip-flops) hold the state (both control and data state) of all of our finite-state machines. In addition to this central role in logic design, flip-flops also consume a large fraction of the die area, power, and cycle time of a typical digital system.

Until now, we have considered a flip-flop as a black box. In this chapter, we study the internal workings of the flip-flop. We derive the logic design of a typical D flip-flop and show how the timing properties introduced in Chapter 15 follow from this design.

We first develop the flip-flop design informally – following an intuitive argument. We start by developing the latch. The implementation of a latch follows directly from its specification. From the implementation we can then derive the setup, hold, and delay times of the latch. We then see how to build a flip-flop by combining two latches in a master–slave arrangement. The timing properties of the flip-flop can then be derived from its implementation.

Following this informal development, we then derive the design of a latch and flip-flop using flow-table synthesis. This serves both to reinforce the properties of these storage elements and to give a good example of flow-table synthesis. We introduce the concept of state equivalence during this derivation. This formal derivation can be skipped by a casual reader.

Combinational logic circuits implement logical functions on a set of inputs. Used for control, arithmetic, and data steering, combinational circuits are the heart of digital systems. Sequential logic circuits (see Chapter 14) use combinational circuits to generate their next state functions.

In this chapter we introduce combinational logic circuits and describe a procedure to design these circuits given a specification. At one time, before the mid 1980s, such manual synthesis of combinational circuits was a major part of digital design practice. Today, however, designers write the specification of logic circuits in a hardware description language (like VHDL) and the synthesis is performed automatically by a computer-aided design (CAD) program.

We describe the manual synthesis process here because every digital designer should understand how to generate a logic circuit from a specification. Understanding this process allows the designer to better use the CAD tools that perform this function in practice, and, on rare occasions, to generate critical pieces of logic manually.