15 - High-level test synthesis

Summary

In this chapter, we concentrate on the register-transfer level (RTL) and behavior level of the design hierarchy.

We first discuss different RTL test generation methods: hierarchical, symbolic, functional, and those dealing with functional fault models. We then discuss a symbolic RTL fault simulation method.

Next, we discuss RTL design for testability (DFT) methods. The first such method is based on extracting and analyzing the control/data flow of the RTL circuit. The second method uses regular expressions for symbolic testability analysis and test insertion. These are followed by high-level and orthogonal scan methods.

Under RTL built-in self-test (BIST), we show that some of the symbolic testability analysis methods used for RTL DFT can also be extended to BIST. Then we discuss a method called arithmetic BIST, and a method to derive native-mode self-test programs for processors.

At the behavior level, we first show how behavioral modifications can be made to improve testability. We also present three types of behavioral synthesis for testability techniques. The first type targets ease of subsequent gate-level sequential test generation. The second type deals with ease of symbolic testability using precomputed test sets of different RTL modules in the circuit. The third type is geared towards BIST.

Introduction

High-level test synthesis refers to an area in which test generation, fault simulation, DFT, synthesis for testability, and BIST are automatically performed at the higher levels, i.e., register-transfer and behavior levels, of the design hierarchy.