Book contents
- Frontmatter
- Dedication
- Contents
- Preface
- 1 Introduction
- 2 Multigate and Nanowire Transistors
- 3 Synthesis and Fabrication of Semiconductor Nanowires
- 4 Quantum Mechanics in One Dimension
- 5 Nanowire Electronic Structure
- 6 Charge Transport in Quasi-1d Nanostructures
- 7 Nanowire Transistor Circuits
- Index
- References
3 - Synthesis and Fabrication of Semiconductor Nanowires
Published online by Cambridge University Press: 05 April 2016
Book contents
- Frontmatter
- Dedication
- Contents
- Preface
- 1 Introduction
- 2 Multigate and Nanowire Transistors
- 3 Synthesis and Fabrication of Semiconductor Nanowires
- 4 Quantum Mechanics in One Dimension
- 5 Nanowire Electronic Structure
- 6 Charge Transport in Quasi-1d Nanostructures
- 7 Nanowire Transistor Circuits
- Index
- References
Summary
Semiconductor nanowires can be fabricated using a variety of techniques. Techniques based on the semiconductor industry legacy of using lithography patterning and material removal methods to etch semiconductor layers into nanowires are called “top-down” fabrication techniques. A typical example is the patterning of photoresist lines on top of a silicon-on-insulator layer followed by the removal of excess silicon using a plasma etch tool in order to create silicon nanowires. Another example is the patterning of an array of “dots” on a silicon substrate and the use of plasma etching to fabricate vertical silicon columns. Techniques based on the direct epitaxial growth of a nanowire from a seeding substrate without using material removal techniques are called “bottom-up” growth techniques. The classical example is the vapor–liquid–solid (VLS) growth of silicon nanowires on a silicon substrate using gold eutectic droplets [1,2].
Top-down fabrication techniques
In this section, the more common “top-down” fabrication techniques are described. They are typically based on process steps used following the semiconductor industry legacy by combining patterning using lithography and material removal using etching tools allowing the shaping of thin semiconductor films into nanowire structures.
Horizontal nanowires
Semiconductor nanowires can be fabricated using either semiconductor-on-insulator wafers or bulk semiconductor wafers. In the case of silicon, nanowires can be made using a silicon-on-insulator (SOI) wafer. The silicon film thickness can be trimmed down to the desired value using oxidation and wet oxide strip in a buffered hydrofluoric acid (HF) solution [3,4]. The lateral dimensions of the nanowire are usually defined using e-beam lithography permitting patterning of very narrow lines [5,6,7]. Other techniques, such as the use of block copolymer self-assembly, can be used to define narrow polymer parallel lines and use them as a template for pattern transfer onto a semiconductor. Directed self-assembly of block copolymers is capable of achieving high-density patterning with critical dimensions approaching 5 nm. High-density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer has been demonstrated. The wires are formed with a pitch of 42 nm resulting in dense arrays (5 × 106 wires/cm) of unidirectional and isolated parallel silicon nanowires on an insulator substrate. This technique demonstrated the fabrication of nanowires with critical dimension ranging down to less than 10 nm [8,9].
- Type
- Chapter
- Information
- Nanowire TransistorsPhysics of Devices and Materials in One Dimension, pp. 54 - 80Publisher: Cambridge University PressPrint publication year: 2016
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