Preface

Summary

Computer architecture is at a turning point. Radical changes occurred in the 1980s when the Reduced Instruction Set Computer (RISC) philosophy, spurred in good part by academic research, permeated the industry as a reaction to the Complex Instruction Set Computer (CISC) complexities. Today, three decades later, we have reached a point where physical limitations such as power dissipation and design complexity limit the speed and the performance of single-processor systems. The era of chip multiprocessors (CMP), or multicores, has arrived.

Besides the uncertainty on the structure of CMPs, it is not known yet whether the future CMPs will be composed of simple or complex processors or a combination of both and how the on-chip and off-chip memory hierarchy will be managed. It is important for computer scientists and engineers to look at the possible options for the modules that will compose the new generations of multicores. In this book, we describe the architecture of microprocessors from simple in-order short pipe designs to out-of-order superscalars with many optimizations. We also present choices and enhancements in the cache hierarchy of single processors. The last part of this book introduces readers to the state-of-the-art in multithreading and multiprocessing, emphasizing single-chip implementations and their cache hierarchy.

The emphasis in this book is on “how things work” at a black box and algorithmic level. It is not as close to the hardware as books that explain features at the register transfer level.