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from Part II - DPST circuit issues
Published online by Cambridge University Press: 05 June 2015
DPS transmitters are not restricted to only having DPS operation at the final transmitter stage. Under the right conditions there can be significant advantages to operating multiple stages in the transmitter with dynamic power supplies. And under the wrong conditions, an attempt to operate multiple stages as a DPS transmitter can be disastrous. In this chapter, both situations are encountered.
The basic architecture is straightforward, and a three-stage version is shown in Figure 12-1. The most flexibility is provided by simply cascading DPS stages. There are two primary motivations to consider the complexity of extending DPS operation to driver stages. Further improvement of the overall transmitter energy efficiency is the primary motivation. Particularly when polar modulation is used for maximum energy efficiency, DPS operation of earlier stages extends the dynamic range for output envelope accuracy.
Interstage signal magnitude management
Multistage design exists because overall gain requirements in product design exceed the gain capabilities of a single stage. The power consumption of earlier stages must be progressively lower for this strategy to make sense. Ohm's Law shows that there are not many degrees of freedom to achieve this goal: if the supply voltage is unchanged, then the load resistances must progressively increase. If the stage load resistances stay the same, then the supply voltages must progressively decrease.
Examination of the interstage design issues points out significant differences in design objectives. When a bipolar transistor is being driven, the driving stage must provide sufficient base current to (1) drive the required collector current through the transistor β action, and (2) provide the CBE current that shunts the transistor action as discussed in Section 7.3.1 and shown in Figure 7-15. Along with VBE and rπ, this current establishes the input impedance of the transistor at the operating frequency. Design of the interstage matching network (InMN) in Figure 12-2(a) must convert the signal at the output of the driver to this resistive and reactive current and voltage.
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