Appendix 1.4 - CMOS reduces logic gate power dissipation

Summary

Digital processing needs lots of logic gates. MOSFET transistors, as noted in the main text, are the preferred way to create them. However, owing to excessive current leakage, early gates built with MOSFETs suffered from high power dissipation. Put millions of these devices on a chip and the constant current drain could cause overheating.

The CMOS architecture provided the solution to this problem, at the expense of more complex chip manufacturing, by dramatically reducing the gate power dissipation, enabling very large scale integrated circuits.

To demonstrate the principle behind CMOS, let's examine the differences between a simple inverter gate built without this architecture and one built with it.

We start with the non-CMOS inverter built with just one kind of MOSFET. As Figure A-1.4.1 shows, two n-channel transistors are interconnected with the source of the bottom transistor connected to the drain of the top transistor. The top transistor is always on since its gate is always connected to the battery.

Look at the left side of the figure. When a value of 10 volts (the input voltage) is applied to the bottom transistor gate, a (1), it turns on, forming a conducting path from battery to ground. Therefore, the output voltage is zero, indicating a (0) state.

Now look at the right side of the figure. The input gate voltage is zero, the bottom transistor is off, and the output is connected to the battery through the top transistor. Hence the output voltage is 10 volts, a (1).