Book contents
- Frontmatter
- Contents
- List of contributors
- 1 Model checking and equivalence checking
- 2 Transaction-level system modeling
- 3 Response checkers, monitors, and assertions
- 4 System debugging strategies
- 5 Test generation and coverage metrics
- 6 SystemVerilog and Vera in a verification flow
- 7 Decision diagrams for verification
- 8 Boolean satisfiability and EDA applications
- Index
5 - Test generation and coverage metrics
Published online by Cambridge University Press: 05 August 2012
- Frontmatter
- Contents
- List of contributors
- 1 Model checking and equivalence checking
- 2 Transaction-level system modeling
- 3 Response checkers, monitors, and assertions
- 4 System debugging strategies
- 5 Test generation and coverage metrics
- 6 SystemVerilog and Vera in a verification flow
- 7 Decision diagrams for verification
- 8 Boolean satisfiability and EDA applications
- Index
Summary
Introduction
Digital circuits are usually produced following a multi-step development process composed of several intermediate design phases. Each one is concluded by the delivery of a model that describes the digital circuit in increasing detail and with different abstraction levels. The first design step usually produces the highest abstraction level model, which describes the general behavior of the circuit leaving internal details out; whereas the last steps provide lower-level descriptions, with more detail and closer to the actual implementation of the circuit. Clearly, the lower the abstraction level, the higher the complexity of the resulting model.
In the following, some of the main characteristics of the most commonly adopted design abstraction levels as well as the main features of the delivered models at each level will be sketched. It is important to note that levels of abstraction higher or lower than those described here could also exist in a design cycle; but we only focus on the most commonly adopted ones.
• Architectural level
This is often the highest abstraction level: the circuit model delivered here is used as a reference since it contains few implementation details. The main goal at the architectural level is to provide a block architecture of the circuit implementing the basic functional specifications. The delivered model is usually exploited to evaluate the basic operations of the design and the interactions among the components within the system. At this design level, a complete simulatable model may be built in some high-level language; typically, these models do not contain timing information.
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- Type
- Chapter
- Information
- Practical Design Verification , pp. 122 - 153Publisher: Cambridge University PressPrint publication year: 2009