In this article, a low phase noise signal source to be used as local oscillator in pulse Doppler radio frequency (PDRF) sensor is proposed. Innovative design techniques for realization of the low phase noise frequency source using phase-locked loop (PLL) and dielectric resonator (DR) are presented. Qualitative investigations have been carried out on the effect of phase noise in PDRF sensor performance. An X-band vibration resistant PLL-based frequency source with phase noise better than −95 dBc at 1 kHz frequency offset has been designed here. It also presents the design of a 7.6 GHz low phase noise, vibration resistant DR oscillator. Systematic analysis of the key design aspects, their thermal-vibrational stability, and ease of integration with hybrid microwave integrated circuits have been disclosed. A prototype board is fabricated, assembled in a compact mechanical enclosure of dimension 55 × 55 × 15 mm3. Finally, developed module is experimentally validated under 7.6 g rms magnitude random vibration test in three axes and compared results with other state of-the-art similar works. The comparison clearly shows the merit of present research work over other similar existing works.

Gain-parameter-dependent transfer functions and phase-noise performances in a mode-locked Yb-doped fiber laser are measured in this study. It is discovered that the corner frequency in the amplitude and phase domains is determined by the absorption coefficient of the gain fiber, when the total absorption and other cavity parameters are fixed. This shows that an oscillator using gain fiber with higher dopant concentration accumulates more phase noise. Furthermore, we present net cavity dispersion-dependent transfer functions to verify the effect of dispersion management on the frequency response. We derive a guideline for optimizing mode-locked fiber laser design to achieve low phase noise and timing jitter.

The purpose of this paper is to disclose improved crystal based frequency source system covering design techniques and experimental methodologies for the stabilization of phase noise performance of X-band phase-locked loop (PLL) at 10.6 GHz. Phase noise performance of PLL-based unit under test (UUT) is prone to disturbance occurred in random vibration profile frequency spectrum. UUT self-resonance plays vital role in occurrence of disturbance in random vibration profile. The stabilization of phase noise performance during dynamic (random) vibration condition is achieved by following methodologies, i.e. vibration-isolator compensation techniques, purification tactic for reference crystal of PLL, and spatial location analysis for finding out mounting position of reference crystal. Spatial analysis helps to filter out UUT self-resonance frequency from random vibration spectrum which leads to reduction of frequency resonance pickups during random vibration testing.

The implementation of advanced multi-level modulation schemes such as quadrature phase-shift keying (QPSK) in contrast to the conventional on–off keying is crucial to further boost the terahertz (THz) communications speed. Thereby, carrier phase noise reduction in the THz range is one of the key goals that need to be urgently achieved. In this paper, the photonic-based THz sources and the phase noise problem are briefly summarized. Then, a low phase-noise photonic source based on the stimulated Brillouin scattering (SBS) optical fiber cavity is first applied for a 300-GHz-band QPSK wireless communication link. The highest data rate at forward-error-correction limited condition was 15 Gbaud utilizing the SBS-based photonic source with a small transmit power of ~ −36 dBm. Its transmission characteristics are evaluated and compared with the conventional optical frequency comb generator (OFCG)-based source at 5 Gbaud. The proposed SBS-based photonic source has been proven to offer better performances than the OFCG-based source with respect to the phase noise, optical carrier to noise ratio, and bit error rate in communications.

In this paper, the design theory of an 8 GHz oscillator with a new structure of active dielectric resonator (DR) is presented. The new structure emphasizes on phase noise reduction by using only one active device. The proposed structure uses additional feedback from transistor to resonator in order to increase the quality factor. Measurement results report that phase noise is reduced to −145.19 dBc/Hz at 100 kHz offset frequency which represents 12 dB improvement compared with oscillators with passive DR. Also, in comparison with conventional active resonator oscillators, noise source of the second amplifier which makes spurious oscillation is removed. The size and power consumption are reduced due to the use of a single transistor. This structure has the lowest phase noise in comparison with other DR oscillators. In order to implement the proposed oscillator, a circuit including amplifier, resonator, coupler, and phase shifter is designed and realized.

We present a technique allowing the stabilization and tuning of a modulation sideband in the presence of high-carrier frequency jitter and increased carrier phase noise. This technique is of particular interest in communication systems where oscillators providing the carrier signal cannot be stabilized by a conventional phase-locked loop, such as systems relying on low-cost optical LO generation techniques. The results obtained in simulation are validated by measurements carried out on a modular system demonstrator.

The design of a 61.44 GHz integrated Phase-locked loop (PLL) on a 180 GHz BiCMOS technology is presented. The PLL was optimized for a very fast settling time of 4 µs as required by the system specifications. Because the receiver is using a carrier recovery circuit that can follow the slow changes of the carrier such as phase noise, the sensitivity of the bit error rate to phase noise at the receiver end is very low. As a result, to achieve the required dynamic behavior, the phase noise performance could be sacrificed and the loop bandwidth was increased until the needed settling time was achieved, while taking the suppression of the reference spurs into consideration. Capacitor multiplication was used to enable the integration of the loop filter (LF) on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. In addition, a very close matching between the measured and simulated phase noise of the system was achieved. The PLL consumes a power of 200 mW from 2 and 3 V supply voltages, while delivering a differential output power of −7 dBm, sufficient to drive the following I/Q modulator without additional amplification.

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

This paper proposes a receiver that repeats iterative frequency-domain equalization (FDE) and decision-directed phase noise compensation (DD-PNC) to alleviate degradation due to the phase noise for millimeter-wave single carrier (SC) systems. High bit-rate SC-FDE transceivers based on the single-chip Si RF-CMOS IC technology in the 60-GHz millimeter-wave band have been extensively studied for wireless personal area network (WPAN) systems, and the relatively large phase noise in a phase-locked loop (PLL) synthesizer severely degrades transmission performance. In an initial processing of the proposed receiver, a cyclic prefix (CP)-based phase noise compensator (CP-PNC) removes the phase noise from a time-domain received signal by using CP, which is known to the receiver, and the channel is equalized by the iterative FDE using the conventional minimum mean-square-error (MMSE) weight. In an iterative processing, DD-PNC estimates the phase noise each symbol by exploiting an output of a channel decoder, and then compensates the time-domain received signal for the phase noise by using the estimate. In order to equalize the compensated received signal, the iterative FDE performs both the MMSE filtering and residual inter-symbol interference cancelation using the decoder output. Computer simulations following the 60-GHz WPAN standard demonstrate that in the 64QAM with the coding rate of 3/4, the proposed receiver with three iterations can drastically remove the phase noise of −85 dBc/Hz at 1 MHz offset, and that it can achieve excellent transmission performance.

This article addresses the analysis and digital signal processing (DSP)-based mitigation of phase noise and sampling clock jitter in orthogonal frequency division multiplexing (OFDM) radios. In the phase noise studies, the basic direct-conversion receiver architecture case is assumed with noisy downconverting oscillator. In the sampling jitter case, on the other hand, the so-called direct-radio-frequency-sampling receiver architecture is deployed utilizing bandpass sub-sampling principle. The basis for the DSP-based impairment mitigation techniques is first formed using analytical receiver modeling with incoming OFDM waveform, where the effects of both oscillator phase noise and sampling clock jitter are mapped to certain type subcarrier cross-talk and distortion compared to ideal receiver case. Then iterative detection principles and interpolation techniques are developed to essentially estimate and cancel the subcarrier distortion. Also some related practical aspects, like channel estimation, are addressed. The performance of the proposed mitigation techniques is analyzed and verified with extensive computer simulations. In the simulations, realistic phase-locked-loop-based oscillator models are used for phase noise and sampling clock jitter. In addition, different received signal conditions like plain additive white Gaussian noise channel and extended ITU-R Vehicular A multipath channel are considered for practical purposes. Altogether the obtained results indicate that the effects of oscillator and sampling clock instabilities can be efficiently reduced using the developed signal processing techniques.