In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.

In this work, a high-efficiency radio-frequency energy-harvesting system that takes use of the Portuguese Digital Television signal (750–758 MHz) to obtain DC power is proposed. To be useful, it is optimized to operate at low-power conditions. For the rectifier, three different solutions are presented: a single-series diode, a single-shunt diode, and a voltage-doubler configuration. The efficiency is similar for the three rectifiers – about 54% with a sine-wave excitation and −10.5 dBm of input power. Field measurements with the voltage-doubler have shown 63% efficiency for the same input power.

A highly integrated Ku-band (10.7–12.75 GHz) planar phased array receiver of 64 antenna elements is presented. It features instantaneous reception of the full Ku-band (2.05 GHz wide) in two orthogonal polarizations with wide scan angles by using time delay instead of phase shift. The receiver is part of a system for satellite broadcast TV reception on board of moving vehicles. Two SiGe radio frequency integrated circuits (RFICs) were developed, packaged in ceramic BGAs and assembled onto a 15-layer printed circuit board (PCB) which integrates the antenna elements. An outline of the system is given along with a detailed description. It sets a new standard in integration density. The receiver has extensive analog signal processing at intermediate frequency (IF)-level. A novel bipolar implementation for true time delay is proposed, with a continuous programmable delay range of 0…80 ps with less than 2.5 ps group-delay variation in 2 GHz bandwidth (BW). The wide BW calls for a constant group-delay implementation in the IF chain. The receiver (RFIC) consumes only 132 mW per channel. Each channel has 40 dB gain.

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.