Power amplifier (PA) nonlinearities and the digital predistortion (DPD) required for linearization are modeled at baseband using the memoryless polynomial, memory polynomial, and pruned Volterra series. The sampling requirements for the nonlinear basis waveforms created from a band-limited signal are determined as a function of the polynomial order. A Gaussian approximation of the channel filtering is used to make the mathematical analysis tractable. For the memory polynomial and pruned Volterra series cases, the spacing between memory taps, referred to as the delay offset, is selected to trade off model accuracy and the condition number of the coefficient estimation. Examples are provided showing how to select the appropriate delay offset for a memory-based amplifier model and its effect on the DPD performance. A pruned Volterra series is proposed, which demonstrates improved DPD performance compared with the memory polynomial.

This paper expounds the systematic modeling of the behavior of radio frequency (RF) power amplifiers (PAs) exhibiting nonlinear, dynamic behavior. The approach begins with an analysis of the PA output signal to deduce the minimum embedding parameters required to accurately model its response, particularly the nonlinearity order and memory effects depth. The knowledge of the RF PA is then exploited in limiting the number of kernels consequently addressing the complexity of the Volterra series which has been the key hindrance to its wider practical adoption. In the proposed Volterra series model, performance is assessed and compared to memory polynomial model and dynamic deviation reduction Volterra models when used to linearize different high-power amplifiers driven with wideband signals of bandwidth up to 40 MHz. Significant linearization performance is achieved using a reduced number of kernels.

This paper presents a new order selection technique of matrix memory polynomial technique that models the nonlinearities of single-branch and multi-branch transmitters. The new criteria take into account the complexity of the model in addition to its mean-square error in the selection criteria. The quasi-convexity of the proposed criteria was proven in this work. By using this proposed Akaike information criterion (AIC) and Bayesian information criterion (BIC) criteria, the model order selection was cast as a cost minimization problem. To minimize the criteria, modified gradient descent and simulated annealing algorithms were utilized which resulted in a considerable reduction in the number of search iterations. The performances of the criteria were shown by comparing the normalized mean square error (NMSE) of a higher-order model and the optimum model. It has been shown that the NMSE difference is <0.5 dB, but the complexity is much smaller.

Most non-linear behavioral models of amplifiers are based on functions that are analytic at the origin and thus can be replaced by their Taylor series development around this point, e.g. polynomials of the input signal. Chebyshev Transforms can be used to compute the harmonic response of the model to a sine input signal. These responses are polynomials of the input signal amplitude. A second application of the Chebyshev transform to the first harmonic response or radio frequency (RF) characteristic will lend the carriers and intermodulation (IM) products for a two-carrier input signal, again polynomials. An important class of non-analytic non-linear behavior encountered in practice, such as hard limiters and detectors are either empirically treated or only approximated by an analytic function such as the hyperbolic tangent. This work proposes to generalize the polynomial non-linearity theory by adding non-analytic at the origin functions that, like polynomials, are invariant elements of the Chebyshev Transform. Devices modeled with these non-analytic at the origin functions exhibit intermodulation behavior significantly different from that of classical polynomial models, giving theoretical foundation to a number of important unexplained practical measurement observations.

This paper presents a new macro modeling methodology for solid-state power amplifiers (SSPAs) and packaged transistors used in communication systems. The model topology is based on the principle of harmonic superposition recently introduced by Agilent Technologies' X-parametersTM combined with dynamic Volterra theory. The resulting multi-harmonic bilateral model takes into account the coupling effects of both short- and long-term memory in SSPAs. In this work, the behavioral model was developed from time-domain load pull and used to simulate the amplifier's response to a 16-QAM signal with specific regards to ACPR and IM3.

In this paper, a complete design procedure, together with robust system validation approaches, is presented for implementing a high-performance re-configurable digital predistortion (DPD) test platform for compensating for nonlinear distortion and memory effects induced by radio frequency (RF) power amplifiers (PAs) in the transmitters of modern wireless communication systems. This hardware and software co-operated test system not only enables effective validation for DPD algorithm development, but also provides a high-performance and reliable hardware-based linearization test platform. The experimental test was applied on a medium power Doherty amplifier, which was designed for 3 G/4 G wireless communication base stations. By applying our DPD algorithms on the proposed platform, more than 30 dB improvements in adjacent channel power ratio can be achieved for Universal Mobile Telecommunications System and long-term evolution signal excitations.

Digital predistortion (DPD) of a nonlinear power amplifier (PA) is made challenging when the observation bandwidth (OBW) used to measure the output signal is narrower than the intermodulation distortion (IMD) spectrum generated. Wide bandwidth input signals stimulate memory effects within the PA thereby requiring the model order of the DPD to be expanded to include memory correction coefficients. However, if the model order is over-specified relative to the OBW, the estimation of the DPD coefficients will be ill-conditioned and the distortion cancellation will be degraded. This paper proposes a method of selecting the best model order of the DPD coefficient estimation for the available OBW. Adjacent channel power ratio (ACPR) is used as an independent measure of the distortion cancellation for a given model order. Experimental results demonstrate the relationship between the model order of the estimation, the OBW, and the ACPR performance of the wide bandwidth IMD cancellation.

In many base-station applications, the load/usage fluctuates over time periods of hours to days, thereby varying the required transmit power by as much as 10 dB. It is desirable to maintain high efficiency and linearity in the power amplifier under these back-off conditions in order to achieve high long-term efficiency. This paper demonstrates a scalable digital predistortion (DPD) approach that can be applied under different power back-off levels in envelope-tracking (ET) amplifiers and quantifies the associated efficiency. Efficiency comparisons are made with other amplifier configurations such as Class B and Doherty. Efficiency of 60% at full power (35 W average power) and >30% efficiency at 10 dB average power back-off are measured in an ET amplifier with a 7.54 dB peak-to-average ratio (PAPR) single-carrier WCDMA signal while meeting linearity specifications. Long-term base-station usage probability functions are presented. The long-term efficiency of the ET amplifiers is simulated to be greater than that of Class B and Doherty amplifiers.

This paper describes a digital signal processing (DSP) method for achieving “ideal” amplification, maximizing both the average output signal power and power-added-efficiency for any signal waveform and any power amplifier (PA) transfer characteristic. Detailed algorithms are described for optimally accomplishing peak reduction (PR), predistortion (PD) linearization, and integration of these DSP techniques with envelope tracking PAs. Hardware characterization results validate the theories of PD and PR operation.

This paper presents and discusses two possible real-time digital predistortion (DPD) architectures suitable for envelope tracking (ET) power amplifiers (PAs) oriented at a final computationally efficient implementation in a field programmable gate array (FPGA) device. In ET systems, by using a shaping function is possible to modulate the supply voltage according to different criteria. One possibility is to use slower versions of the original RF signal's envelope in order to relax the slew-rate (SR) and bandwidth (BW) requirements of the envelope amplifier (EA) or drain modulator. The nonlinear distortion that arises when performing ET with a supply voltage signal that follows both the original and the slow envelope will be presented, as well as the DPD function capable of compensating for these unwanted effects. Finally, two different approaches for efficiently implementing the DPD functions, a polynomial-based and a look-up table-based, will be discussed.