Silicon Interposer Reliability Optimization through Process-Oriented Stress Modeling

Abstract

A process-oriented stress modeling methodology is developed to investigate the stress evolution during the silicon interposer packaging process. An FEM based 3D TCAD simulator is used to perform the process steps to construct the silicon interposer stack in sequential order. These steps include TSV fabrication for passive silicon interposer, micro-bumping and reflow process for integrating active dies and passive interposer, C4-bumping and reflow for interposer BT-substrate stacking, and epoxy mold curing for interposer encapsulation. Stress simulations are carried out for each process step to obtain accurate stress evolution history. To resolve micron features within millimeter structures, the modeling strategy employs symmetry conditions, and equivalent materials for regions away from structure features of interest. The detailed structure includes 3x3 arrays of microbumps, TSV arrays, and C4-bumps with multiple material layers at the stack corner. Important design parameters include interposer thickness and edge clearance. For different silicon interposer configurations critical stresses in the outmost microbump and C4-bump are analyzed and compared. The reliability implications are discussed.