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Computationally efficient real-time digital predistortion architectures for envelope tracking power amplifiers

Published online by Cambridge University Press:  05 March 2013

Pere L. Gilabert  and
Gabriel Montoro
Pere L. Gilabert*
Affiliation:
Department of Signal Theory and Communications, Universitat Politècnica de Catalunya-BarcelonaTech, c/ Esteve Terradas 7, 08860 Castelldefels, Barcelona, Spain
Gabriel Montoro
Affiliation:
Department of Signal Theory and Communications, Universitat Politècnica de Catalunya-BarcelonaTech, c/ Esteve Terradas 7, 08860 Castelldefels, Barcelona, Spain
*
Corresponding author: Pere L. Gilabert Email: [email protected]
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Abstract

This paper presents and discusses two possible real-time digital predistortion (DPD) architectures suitable for envelope tracking (ET) power amplifiers (PAs) oriented at a final computationally efficient implementation in a field programmable gate array (FPGA) device. In ET systems, by using a shaping function is possible to modulate the supply voltage according to different criteria. One possibility is to use slower versions of the original RF signal's envelope in order to relax the slew-rate (SR) and bandwidth (BW) requirements of the envelope amplifier (EA) or drain modulator. The nonlinear distortion that arises when performing ET with a supply voltage signal that follows both the original and the slow envelope will be presented, as well as the DPD function capable of compensating for these unwanted effects. Finally, two different approaches for efficiently implementing the DPD functions, a polynomial-based and a look-up table-based, will be discussed.

Keywords

Power amplifiers and linearizersModelingSimulation and characterizations of devices and circuits
Type
Research Papers
Information
International Journal of Microwave and Wireless Technologies , Volume 5 , Special Issue 2: Special Issue on Power Amplifier Linearization , April 2013 , pp. 187 - 193
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2013

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