Skip to main content Accessibility help
×
Hostname: page-component-78c5997874-dh8gc Total loading time: 0 Render date: 2024-11-05T03:35:14.450Z Has data issue: true hasContentIssue false

Bibliography

Published online by Cambridge University Press:  19 February 2018

Nicola Da Dalt
Affiliation:
Intel Corporation
Ali Sheikholeslami
Affiliation:
University of Toronto
Get access

Summary

Image of the first page of this content. For PDF version, please use the ‘Save PDF’ preceeding this image.'
Type
Chapter
Information
Understanding Jitter and Phase Noise
A Circuits and Systems Perspective
, pp. 242 - 248
Publisher: Cambridge University Press
Print publication year: 2018

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] A., Papoulis and S. U., Pillai, Probability, Random Variables and Stochastic Processes, 4th ed. McGraw-Hill, 2002.
[2] “ITU-T Recommendation G.810: Definitions and Terminology for Synchronization Networks,” International Telecommunication Union (ITU), 1996.
[3] S., Bregni, “Measurement ofMaximum Time Interval Error for Telecommunications Clock Stability Characterization,” IEEE Transactions on Instrumentation and Measurement, vol. 45, no. 5, pp. 900–906, Oct. 1996.
[4] “Definition of Skew Specifications for Standard Logic Devices,” JEDEC Standard JESD65B, 2003.
[5] T. C., Weigandt, B., Kim, and P. R., Gray, “Analysis of Timing Jitter in CMOS Ring Oscillators,” Proceedings of the International Symposium on Circuits and Systems (ISCAS), vol. 4, pp. 27–30, 1994.
[6] A., Demir, A., Mehrotra, and J., Roychowdhury, “Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterization,IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 47, pp. 655–674, May 2000.
[7] “Understanding SYSCLK Jitter,” Freescale, Tech. Rep., Feb. 2010, application Note AN4056.
[8] E., Pineda, “Clocks Basics in 10 Minutes or Less,” Texas Instruments, Tech. Rep., 2010, webinar.
[9] D. C., Lee, “Analysis of Jitter in Phase-Locked Loops,IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 49, no. 11, pp. 704–711, Nov. 2002.
[10] F., Herzel and B., Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 46, pp. 56–62, Jan. 1999.
[11] W., Kester, The Data Conversion Handbook. Newnes, 2004, Analog Devices Series.
[12] ——, “Aperture Time, Aperture Jitter, Aperture Delay Time – Removing the Confusion,” Analog Devices, Tech. Rep., 2009, tutorial MT-007.
[13] R. E., Walpole, R. H., Myers, S. L., Myers, and K., Ye, Probability and Statistics for Engineers and Scientists. Prentice-Hall, 2007.
[14] B., Ham, “Fibre Channel – Methodologies for Jitter and Signal Quality Specification,” International Committee for Information Technology Standardization (INCITS), Jun. 2005.
[15] M. P., Li, Jitter, Noise, and Signal Integrity at High-Speed. Prentice-Hall, 2008.
[16] G., Hänsel, K., Stieglbauer, G., Schulze, and J., Moreira, “Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE,” IEEE International Test Conference (ITC04), pp. 1303–1312, Oct. 2004.
[17] D., Hong and K.-T., Cheng, “An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing,” IEEE Asian Test Symposium (ATS07), vol. 224–229, Oct. 2007.
[18] J. L., Huang, “A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter,” IEEE Asian Test Symposium (ATS06), vol. 318–326, Nov. 2006.
[19] M., Li, J., Wilstrup, R., Jessen, and D., Petrich, “A New Method for Jitter Decomposition Through Its Distribution Tail Fitting,” IEEE International Test Conference (ITC99), pp. 788–794, Sep. 1999.
[20] R., Stephens, “Separation of Random and Deterministic Components of Jitter,” US Patent 7 149 638, Dec. 2006.
[21] ——, “Separation of a Random Component of Jitter and a Deterministic Component of Jitter,” US Patent 7 191 080, Mar. 2007.
[22] S., Wisetphanichkij and K., Dejhan, “Jitter Decomposition by Derivatived GaussianWavelet Transform,IEEE International Symposium on Communication and Information Technology (ISCIT04), vol. 2, pp. 1160–1165, Oct. 2004.
[23] S., Erb and W., Pribyl, “Design and Performance Considerations for an On-Chip Jitter Analysis System,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3969–3972, May 2010.
[24] “IEEE Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology – Random Instabilities,” IEEE Std 1139–2008, Feb. 2008.
[25] A., Hajimiri and T. H., Lee, The Design of Low Noise Oscillators. Kluwer Academic Publishers, 1999.
[26] A., Lacaita, S., Levantino and C., Samori, Integrated Frequency Synthesizers for Wireless Systems. Cambridge University Press, 2007.
[27] G., Marzin, S., Levantino, C., Samori and A., Lacaita, “A Background Calibration Technique to Control Bandwidth in Digital PLLs,” Proceedings of the International Solid State Circuit Conference, pp. 54–55, Feb. 2014.
[28] E., Temporiti, C.Weltin-Wu, D., Baldi, R., Tonietto, and F., Svelto, “A 3GHz Fractional All- Digital PLLWith a 1.8MHz Bandwidth Implementing Spur Reduction Techniques,IEEE Journal of Solid State Circuits, vol. 44, no. 3, pp. 824–834, Mar. 2009.
[29] C., Samori, A. L., Lacaita, A., Zanchi, and F., Pizzolato, “Experimental Verification of the Link Between Timing Jitter and Phase Noise,Electronics Letters, vol. 34, no. 21, pp. 2024–2025, Oct. 1998.
[30] M., Abramowitz and I., Stegun, Eds., Handbook of Mathematical Functions with Formulas, Graphs, and Mathematical Tables. Dover, 1965.
[31] C., Liu and J. A., McNeill, “Jitter in Oscillators with 1/f Noise Sources,IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 773–776, 2004.
[32] A., Demir, “Computing Timing Jitter from Phase Noise Spectra for Oscillators and Phase- Locked Loops with White and 1/f Noise,IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 9, pp. 1869–1884, Sep. 2000.
[33] A., Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” IEEE Journal of Solid State Circuits, pp. 1803–1816, Aug. 2006.
[34] W., Sansen, Analog Design Essentials. Springer, 2006.
[35] T., Pialis and K., Phang, “Analysis of Timing Jitter in Ring Oscillators Due to Power Supply Noise,IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 685– 688, 2003.
[36] A., Strak and H., Tenhunen, “Analysis of Timing Jitter in Inverters Induced by Power- Supply Noise,” International Conference on Design and Test of Integrated Systems in Nanoscale Technology, pp. 53–56, 2006.
[37] J. A., McNeill, “Jitter in Ring Oscillators,IEEE Journal of Solid State Circuits, vol. 32, no. 6, pp. 870–879, Jun. 1997.
[38] R., Navid, T. H., Lee, and R. W., Dutton, “Minimum Achievable Phase Noise of RC Oscillators,IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 630–637, Mar. 2005.
[39] A., Abidi and R. G., Meyer, “Noise in Relaxation Oscillators,” IEEE Journal of Solid State Circuits, pp. 794–802, Dec. 1983.
[40] B., Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of Solid State Circuits, pp. 331–343, Mar. 1996.
[41] J. R., Westra, “High-Performance Oscillators and Oscillator Systems,” PhD dissertation, Delft University of Technology, Delft University Press, 1998.
[42] S. L. J., Gierkink, “Control Linearity and Jitter of Relaxation Oscillators,” PhD dissertation, University of Twente, 1999.
[43] D. B., Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,Proceedings of the IEEE, vol. 54, pp. 329–330, Feb. 1966.
[44] J., Craninckx, “Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks,IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 42, pp. 794–804, Dec. 1995.
[45] A., Hajimiri and T. H., Lee, “Design Issues in CMOS Differential LC Oscillators,IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.
[46] D., Ham and A., Hajimiri, “Concepts andMethods in Optimization of Integrated LC VCOs,IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 896–909, Jun. 2001.
[47] J., Vig, “Quartz Crystal Resonators and Oscillators,” IEEE Ultrasonics, Ferroelectrics and Frequency Control Society, Tech. Rep., 2004. [Online]. Available: www.ieee-uffc.org/ frequency-control/learning-vig-tut.asp
[48] E., Vittoz, M., Degrauwe, and S., Bitz, “High Performance Crystal Oscillator Circuits: Theory and Application,IEEE Journal of Solid-State Circuits, vol. 23, no. 3, pp. 774–783, Jun. 1988.
[49] A., Hajimiri and T. H., Lee, “A General Theory of Phase Noise in Electrical Oscillators,IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[50] ——, “Corrections to ‘A General Theory of Phase Noise in Electrical Oscillators’,IEEE Journal of Solid-State Circuits, vol. 33, p. 928, Jun. 1998.
[51] A., Hajimiri, S., Limotyrakis, and T. H., Lee, “Jitter and Phase Noise in Ring Oscillators,IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 790–804, Jun. 1999.
[52] L., Lu, Z., Tang, P., Andreani, A., Mazzanti, and A., Hajimiri, “Comments on ‘Comments on “A General Theory of Phase Noise in Electrical Oscillators”’,IEEE Journal of Solid-State Circuits, vol. 43, no. 9, p. 2170, Sep. 2008.
[53] A., Mazzanti and P., Andreani, “Class-C Harmonic CMOS VCOs, with a General Result on Phase Noise,IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2716–2728, Dec. 2008.
[54] J., Bank, “A Harmonic-Oscillator Design Methodology Based on Describing Functions,” PhD dissertation, Chalmers University, Sweden, 2006.
[55] D., Murphy, J. J., Rael, and A. A., Abidi, “Phase Noise in LC Oscillators: A Phasor-Based Analysis of a General Result and of Loaded Q,IEEE Journal of Solid-State Circuits, vol. 57, no. 6, pp. 1187–1203, Jun. 2010.
[56] C., Samori, A. L., Lacaita, F., Villa, and F., Zappa, “Spectrum Folding and Phase Noise in LC Tuned Oscillators,IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 45, no. 7, pp. 781–790, Jul. 1998.
[57] P., Andreani and A., Fard, “More on the 1/f 2 Phase Noise Performance of CMOS Differential-Pair LC-Tank Oscillators,IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2703–2712, Dec. 2006.
[58] P., Andreani, X., Wang, L., Vandi, and A., Fard, “A Study of Phase Noise in Colpitts and LC-Tank CMOS Oscillators,IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp. 1107–1118, May 2005.
[59] E., Hegazi, H., Sjland, and A. A., Abidi, “A Filtering Technique to Lower LC Oscillator Phase Noise,IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1921–1930, Dec. 2001.
[60] M., Garampazzi, P. M., Mendes, N., Codega, D., Manstretta, and R., Castello, “Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator with Transformer-Based Tail Filtering,IEEE Journal of Solid-State Circuits, vol. 50, no. 7, pp. 1657–1668, Jul. 2015.
[61] L., Fanori and P., Andreani, “Class-D CMOS Oscillators,IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3105–3119, 2013.
[62] D., Murphy, H., Darabi, and H., Wu, “A VCO with Implicit Common-Mode Resonance,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 442–443, Feb. 2015.
[63] D., Murphy and H., Darabi, “A Complementary VCO for IoE That Achieves a 195dBc/Hz FOM and Flicker Noise Corner of 200kHz,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 44–45, Feb. 2016.
[64] P. F. J., Geraedts, E. van, Tuijl, E. A. M., Klumperink, G. J. M., Wienk, and B., Nauta, “A 90 uw 12MHz Relaxation Oscillator with a -162db FOM,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 348–618, Feb. 2008.
[65] X., Yang, K., Xu, W., Wang, Y., Uchida, and T., Yoshimasu, “2-GHz Band Ultra-Low-Voltage lc-vco IC in 130nm CMOS Technology,” IEEE International Conference of Electron Devices and Solid–State Circuits, pp. 1–2, Jun. 2013.
[66] P., Dubey, D., Belot, and S., Chatterjee, “Heterogeneous Coupled Ring Oscillator Arrays for Reduced Phase Noise at Lower Power Consumption,” IEEE Asian Solid State Circuits Conference (A-SSCC), pp. 365–368, Nov. 2012.
[67] C.-H., Park and B., Kim, “A Low-Noise, 900MHz VCO in 0.6-μm CMOS,IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 586–591, May 1999.
[68] M. M., Abdul-Latif and E., Sanchez-Sinencio, “Low Phase Noise Wide Tuning Range n-Push Cyclic-Coupled Ring Oscillators,IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1278–1294, Jun. 2012.
[69] C., Li and J., Lin, “A 1 to 9 GHz Linear-Wide-Tuning-Range Quadrature Ring Oscillator in 130 nm CMOS for Non-Contact Vital Sign Radar Application,IEEE Microwave and Wireless Components Letters, vol. 20, no. 1, pp. 34–36, Jan. 2010.
[70] S. W., Park and E., Sanchez-[A-z]+, “RF Oscillator Based on a Passive RC Bandpass Filter,IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3092–3101, Nov. 2009.
[71] S., Levantino, L., Romano, S., Pellerano, C., Samori, and A., Lacaita, “Phase Noise in Digital Frequency Dividers,IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 775–784, May 2004.
[72] A. V., Oppenheim and R. W., Schafer, Discrete-Time Signal Processing, 2nd ed. Prentice- Hall, 1999.
[73] D. J., Kinniment and J. V., Woods, “Synchronization and Arbitration Circuits in Digital Systems,Proceedings of the IEEE, vol. 123, no. 10, pp. 961–966, Oct. 1976.
[74] D. G., Messerschmitt, “Synchronization in Digital System Design,IEEE Journal on Selected Areas in Communications, vol. 8, no. 8, pp. 1404–1419, Oct. 1990.
[75] D. J., Kinniment, “Synchronization and Arbitration in GALS,Electronic Notes in Theoretical Computer Science, vol. 245, pp. 85–101, 2009.
[76] S., Beer, R., Ginosar, R., Dobkin, and Y., Weizman, “MTBF Estimation in Coherent Clock Domains,” IEEE 19th International Symposium on Asynchronous Circuits and Systems, 2013.
[77] N., Da Dalt, M., Harteneck, C., Sandner, and A., Wiesbauer, “On the Jitter Requirements of the Sampling Clock for Analog-to-Digital Converters,IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 49, no. 9, pp. 1354–1360, Sep. 2002.
[78] A., Varzaghani, A., Kasapi, D. N., Loizos, S., Paik, S., Verma, S., Zogopoulos, and S., Sidiropoulos, “A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications,IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3038–3048, Dec. 2013.
[79] L., Kull et al., “A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 378–379, Feb. 2014.
[80] M., El-[A-z]+ and B., Murmann, “General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs,IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 902–910, May 2009.
[81] ——, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC with Background Timing Skew Calibration,IEEE Journal of Solid-State Circuits, vol. 46, no. 4, pp. 838–847, Apr. 2011.
[82] B., Razavi, “Design Considerations for Interleaved ADCs,IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1806–1817, Aug. 2013.
[83] N. L., Dortz, J. P., Blanc, T., Simon, S., Verhaeren, E., Rouat, P., Urard, S. L., Tual, D., Goguet, C., Lelandais-[A-z]+, and P., Benabes, “A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBfs,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 386–388, Feb. 2014.
[84] R., Schreier and G., Temes, Understanding Delta–Sigma Data Converters. John Wiley & Sons, 2005.
[85] T. H., Lee and J. F., Bulzacchelli, “A 155MHz Clock Recovery Delay- and Phase-Locked Loop,IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1736–1746, Dec. 1992.
[86] M. J., Park and J., Kim, “Pseudo-Linear Analysis of Bang-Bang-Controlled Timing Circuits,IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1381–1394, Jun. 2013.
[87] N., Da Dalt, “Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs,IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 11, pp. 1195–1199, Nov. 2006.
[88] G., Balamurugan and N., Shanbhag, “Modeling and Mitigation of Jitter in High-Speed Source-Synchronous Interchip Communication Systems,The Thirty-Seventh Asilomar Conference on Signals, Systems Computers, 2003, vol. 2, pp. 1681–1687, Nov. 2003.
[89] F., Rao and S., Hindi, “Frequency Domain Analysis of Jitter Amplification in Clock Channels,” 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, pp. 51–54, Oct. 2012.
[90] A., Ragab, Y., Liu, K., Hu, P., Chiang, and S., Palermo, “Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links,Journal of Electrical and Computer Engineering, vol. 2011, pp. 1–15, 2011.
[91] B., Casper and F., O'Mahony, “Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links: A Tutorial,IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 1, pp. 17–39, Jan. 2009.
[92] T., Takemoto, H., Yamashita, F., Yuki, N., Masuda, H., Toyoda, N., Chujo, Y., Lee, S., Tsuji, and S., Nishimura, “A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power- Supply-Variation-Tolerant Analog Front End and Data-Format Conversion,IEEE Journal of Solid-State Circuits, vol. 49, no. 2, pp. 471–485, Feb. 2014.
[93] H., Noguchi, N., Yoshida, H., Uchida, M., Ozaki, S., Kanemitsu, and S., Wada, “A 40- Gb/s CDR Circuit with Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback,IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2929–2938, Dec. 2008.
[94] K., Nose, M., Kajita, and M., Mizuno, “A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling,IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2911–2920, Dec. 2006.
[95] T., Hashimoto, H., Yamazaki, A., Muramatsu, T., Sato, and A., Inoue, “Time-to-Digital Converter with Vernier Delay Mismatch Compensation for High Resolution On-Die Clock Jitter Measurement,” IEEE Symposium on VLSI Circuits, pp. 166–167, Jun. 2008.
[96] J., Liang, A., Sheikholeslami, H., Tamura, Y., Ogata, and H., Yamaguchi, “A 28Gb/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance,” IEEE International Solid- State Circuits Conference (ISSCC), pp. 122–123, Feb. 2017.
[97] J., Liang, M. S., Jalali, A., Sheikholeslami, M., Kibune, and H., Tamura, “On-Chip Measurement of Clock and Data Jitter with Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs,IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 845–855, Apr. 2015.
[98] H., Takauchi, H., Tamura, S., Matsubara, M., Kibune, Y., Doi, T., Chiba, H., Anbutsu, H., Yamaguchi, T., Mori, M., Takatsu, K., Gotoh, T., Sakai, and T., Yamamura, “A CMOS Multichannel 10Gb/s Transceiver,IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2094–2100, Dec. 2003.
[99] J., Liang, A., Sheikholeslami, H., Tamura, and H., Yamaguchi, “Jitter Injection for On-Chip Jitter Measurement in PI-Based CDRs,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1–4, Apr. 2017.
[100] J. T. J., Penttinen, Ed., The Telecommunications Handbook: Engineering Guidelines for Fixed, Mobile and Satellite Systems. John Wiley & Sons, 2015.
[101] A., Liscidini, L., Fanori, P., Andreani, and R., Castello, “A Power-Scalable DCO for Multi- Standard GSM/WCDMA Frequency Synthesizers,IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 646–656, Mar. 2014.
[102] M., Mikhemar, D., Murphy, A., Mirzaei, and H., Darabi, “A Phase-Noise and Spur Filtering Technique Using Reciprocal-Mixing Cancellation,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 86–87, Feb. 2013.
[103] H. M., Walker and J., Lev, Statistical Inference. Holt Rinehart & Winston, 1953.
[104] S. S., Wilks, Mathematical Statistics. John Wiley & Sons, 1962.
[105] W. W., Hines, D. C., Montgomery, D. M., Goldsman, and C. M., Borror, Probability and Statistics in Engineering. John Wiley & Sons, 2003.
[106] S. S., Wilks, “Determination of Sample Sizes for Setting Tolerance Limits,The Annals of Mathematical Statistics, vol. 12, pp. 91–96, 1941.
[107] H., Freeman, Introduction to Statistical Inference. Addison-Wesley, 1962.
[108] J., Rutman and F. L., Walls, “Characterization of Frequency Stability in Precision Frequency Sources,Proceedings of the IEEE, vol. 79, no. 6, pp. 952–960, Jun. 1991.
[109] D., Sullivan, D., Allan, D., Howe, and F.Walls, “Characterization of Clocks and Oscillators,” National Institute of Standards and Technology (NIST), Tech. Rep., Jan. 1990, Technical Note 1337.
[110] W. J., Riley, “Handbook of Frequency Stability Analysis,” National Institute of Standards and Technology (NIST), Tech. Rep., Jul. 2008, Special Publication 1065.
[111] I., Flinn, “Extent of the 1/f Noise Spectrum,Nature, vol. 219, pp. 1356–1357, Sep. 1968.
[112] Y., Tsividis, Operation and Modeling of the MOS Transistor. Oxford University Press, 1999.
[113] M. A., Caloyannides, “Microcycle Spectral Estimates of 1/f Noise in Semiconductors,Journal of Applied Physics, vol. 45, pp. 307–316, 1974.
[114] W., Schottky, “Small-Shot Effect and Flicker Effect,Physics Review, vol. 28, pp. 74–103, 1926.
[115] J., Bernamont, “Fluctuations in the Resistance of Thin Films,Proceedings of the Physical Society, vol. 49, pp. 138–139, 1937.
[116] B. B., Mandelbrot, “Some Noises with l/f Spectrum, a Bridge Between Direct Current and White Noise,IEEE Transactions on Information Theory, vol. 13, no. 2, pp. 289–298, 1967.
[117] J. J., Brophy, “Low-Frequency Variance Noise,Journal of Applied Physics, vol. 41, pp. 2913–2916, 1970.
[118] M. S., Keshner, “1/f Noise,Proceedings of the IEEE, vol. 70, no. 3, pp. 212–218, Mar. 1982.
[119] I. S., Gradshteyn and I. M., Ryzhik, Table of Integrals, Series, and Products. Academic Press, 2007.
[120] V., Radeka, “1/f Noise in Physical Measurements,” IEEE Transactions on Nuclear Science, pp. 17–35, Nov. 1969.
[121] D., Ham and A., Hajimiri, “Virtual Damping and Einstein Relation in Oscillators,IEEE Journal of Solid-State Circuits, vol. 38, no. 3, pp. 407–418, Mar. 2003.
[122] M. S., Keshner, “Renewal Process and Diffusion Models of 1/f Noise,” PhD dissertation, Massachusetts Institute of Technology, 1975.
[123] F. X., Kaertner, “Analysis ofWhite and f-α Noise in Oscillators,International Journal of Circuit Theory and Applications, vol. 18, pp. 485–519, 1990.
[124] D. C., Montgomery and E. A., Peck, Introduction to Linear Regression Analysis. JohnWiley and Sons, 1991.
[125] A. C., Popovici, “Fast Measurement of Bit Error Rate in Digital Links,IEE Proceedings, vol. 134, no. 5, pp. 439–447, Aug. 1987.
[126] M., Miller, “Estimating Total Jitter Concerning Precision, Accuracy and Robustness,” DesignCon, Feb. 2007.
[127] ——, “Measuring Components of Jitter,” US Patent 7 516 030, Apr. 2009.
[128] S., Erb and W., Pribyl, “Design Specification for BER Analysis Methods Using Built-In Jitter Measurements,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 10, Oct. 2012.
[129] W. A., Gardner, Introduction to Random Processes with Applications to Signals and Systems, 2nd ed. McGraw-Hill, 1989.
[130] D., Halford, J. H., Shoaf, and A. S., Risley, “Spectral Density Analysis: Frequency Domain Specification and Measurement of Signal Stability,” 27th Annual Symposium on Frequency Control, pp. 421–431, Jun. 1973.

Save book to Kindle

To save this book to your Kindle, first ensure [email protected] is added to your Approved Personal Document E-mail List under your Personal Document Settings on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part of your Kindle email address below. Find out more about saving to your Kindle.

Note you can select to save to either the @free.kindle.com or @kindle.com variations. ‘@free.kindle.com’ emails are free but can only be saved to your device when it is connected to wi-fi. ‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.

Find out more about the Kindle Personal Document Service.

Available formats
×

Save book to Dropbox

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Dropbox.

Available formats
×

Save book to Google Drive

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

Available formats
×