Book contents
- Frontmatter
- Contents
- Preface
- 1 An introduction to the simulation of electronic systems
- 2 Electronic computer aided design (ECAD) systems
- 3 Design for testability
- 4 Exercising the design in simulation and test
- 5 Input/output of simulation and specification of models
- 6 Simulation algorithms
- 7 Models and model design
- 8 Timing verification
- 9 Fault simulation
- 10 Simulator features and extensions
- Appendix
- References
- Index
6 - Simulation algorithms
Published online by Cambridge University Press: 05 June 2012
- Frontmatter
- Contents
- Preface
- 1 An introduction to the simulation of electronic systems
- 2 Electronic computer aided design (ECAD) systems
- 3 Design for testability
- 4 Exercising the design in simulation and test
- 5 Input/output of simulation and specification of models
- 6 Simulation algorithms
- 7 Models and model design
- 8 Timing verification
- 9 Fault simulation
- 10 Simulator features and extensions
- Appendix
- References
- Index
Summary
Introduction
There are two approaches to simulation.
Simulate for functional correctness, ignoring all timing considerations, and then use a timing verifier to check that time constraints are met.
Simulate in an environment in which the models include timing. As one can never guarantee that all paths through the logic have been exercised, it may still be advisable to use a timing verifier.
The simplest approach to simulation is to have a separate procedure for every logical element in the network being simulated, and the connections between the elements are then mirrored in the structure of the machine code of the program. The entire structure of the network is thus mirrored in the store of the machine doing the simulation. This takes up a great deal of storage space, but is very fast in running, since there are no lengthy lists to be searched and manipulated.
The amount of storage can be reduced by having only one procedure for each element type, and a small amount of storage for every element holding the element-specific data. In the previous description there is a copy of the procedure for every element which uses it and hence no procedure entry and exit as such. With only one copy each procedure requires a call. Procedure calls need machine states to be saved temporarily and restored on exit. This is expensive in CPU resources.
- Type
- Chapter
- Information
- Simulation in the Design of Digital Electronic Systems , pp. 111 - 149Publisher: Cambridge University PressPrint publication year: 1993