Mixed-Signal CMOS for Wireline Communication Transistor-Level and System-Level Design Considerations
Book contents
- Frontmatter
- Contents
- Preface
- Notation and Acronyms
- 1 Introduction to Wireline Communication
- 2 Electrical Channels
- 3 Decision Circuits
- 4 Equalization
- 5 Electrical-Link Transmitter Circuits
- 6 Electrical-Link Receiver Front-Ends
- 7 Optical Channels and Components
- 8 Optical-Link Transmitter Circuits
- 9 Optical Receivers
- 10 Low-Bandwidth (Equalizer-Based) Optical Receivers
- 11 Advanced Topics in Electrical and Optical Links
- 12 Overview of Synchronization Approaches
- 13 Oscillators
- 14 Phase-Locked Loops and Injection-Locked Oscillators
- 15 Clock and Data Recovery
- Appendix A Frequency Domain Analysis
- Appendix B Noise Analysis
- References
- Index
15 - Clock and Data Recovery
Published online by Cambridge University Press: 05 December 2024
Book contents
- Frontmatter
- Contents
- Preface
- Notation and Acronyms
- 1 Introduction to Wireline Communication
- 2 Electrical Channels
- 3 Decision Circuits
- 4 Equalization
- 5 Electrical-Link Transmitter Circuits
- 6 Electrical-Link Receiver Front-Ends
- 7 Optical Channels and Components
- 8 Optical-Link Transmitter Circuits
- 9 Optical Receivers
- 10 Low-Bandwidth (Equalizer-Based) Optical Receivers
- 11 Advanced Topics in Electrical and Optical Links
- 12 Overview of Synchronization Approaches
- 13 Oscillators
- 14 Phase-Locked Loops and Injection-Locked Oscillators
- 15 Clock and Data Recovery
- Appendix A Frequency Domain Analysis
- Appendix B Noise Analysis
- References
- Index
Summary
With PLLs and ILOs introduced in Chapter 14, this chapter introduces and presents the systems that synchronize clocks to incoming data, known as clock and data recovery (CDR) systems. The chapter starts with an introduction and discussion of the metrics of CDRs. Phase detection is done differently in CDRs compared to PLLs. This is explained before the most common approaches are described. Several options are available to the designer for how phase comparisons should be acted on. These are presented and compared next. The chapter continues with an introduction to baud-rate phase detection schemes built on Mueller–Muller phase detection.
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- Information
- Mixed-Signal CMOS for Wireline CommunicationTransistor-Level and System-Level Design Considerations, pp. 366 - 389Publisher: Cambridge University PressPrint publication year: 2024