Benchmarking alternative device structures for the terascale regime

doi:10.1017/CBO9781107337886.005

3 - Benchmarking alternative device structures for the terascale regime

from Section I - CMOS circuits and technology limits

Published online by Cambridge University Press: 05 February 2015

Zachery A. Jacobson and

Kelin J. Kuhn

Edited by

Tsu-Jae King Liu and

Kelin Kuhn

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Zachery A. Jacobson: Affiliation:
University of California, Berkeley
Kelin J. Kuhn: Affiliation:
Intel Corporation and Cornell University
Tsu-Jae King Liu: Affiliation:
University of California, Berkeley
Kelin Kuhn: Affiliation:
Cornell University, New York

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Summary

Introduction

In this chapter, the devices discussed in Chapter 2 are benchmarked against performance targets set by the International Technology Roadmap for Semiconductors (ITRS), as well as against more conventional ultra-thin body (UTB), gate-all-around (GAA), junctionless accumulation mode (JAM) devices, and thin-film transistors.

The chapter begins with a short introduction to the scaling potential of the various devices used in the benchmarking discussion. The benchmarking metrics are then introduced, followed by the benchmarking results, discussion, and conclusions.

Scaling potential of alternative device structures

High electron mobility transistors (HEMT)

The high electron mobility transistor, or HEMT, increases device mobility by separating charge carriers from the ionized dopant atoms, thus reducing ionized impurity scattering. This is accomplished by confining carriers in an undoped quantum well.

Several groups have addressed the dimensional scaling of HEMTs [1–4]. Using electron beam lithography and multiple etch steps, Waldron et al. showed that it is possible to reduce a HEMT down to 30 nm gate-to-contact spacing, but it is difficult to make the gate length small without improvements to the etch processes [1]. Kharche et al. found that InAs is projected to scale well, as quantum well width scaling brings improvements in Ion/Ioff due to lower Ioff [2]. The reduced well width brings the electron peak closer to the gate, allowing for better gate control. Oh and Wong showed that if issues with gate leakage and process integration at small gate lengths can be solved (along with finding a symmetric p-type device), HEMT devices can have lower delay or lower energy-delay product (EDP) [3]. However, others, including Skotnicki and Boeuf, have shown that when drain-induced barrier lowering (DIBL) and sub-threshold swing (S) are included in an effective current metric, strained silicon performs better than III-V HEMTs [4].

Type: Chapter
Information: CMOS and Beyond
Logic Switches for Terascale Integrated Circuits
, pp. 39 - 55

DOI: https://doi.org/10.1017/CBO9781107337886.005 [Opens in a new window]

Publisher: Cambridge University Press

Print publication year: 2015

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References

Waldron, N., Kim, D.-H., & del Alamo, J. A., “A self-aligned InGaAs HEMT architecture for logic applications.” IEEE Transactions on Electron Devices, 57, 297–304 (2010).CrossRef Google Scholar

Kharche, N., Klimeck, G., Kim, D.-H., del Alamo, J. A., & Luisier, M., “Performance analysis of ultra-scaled InAs HEMTs.” In Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1–4 (2009).

Oh, S. & Wong, H.-S. P., “Effect of parasitic resistance and capacitance on performance of InGaAs HEMT digital logic circuits.” IEEE Transactions on Electron Devices, 56, 1161–1164 (2009).CrossRef Google Scholar

Skotnicki, T. & Boeuf, F., “How can high mobility channel materials boost or degrade performance in advanced CMOS.” In VLSI Technology (VLSIT), 2010 Symposium on, pp. 153–154 (2010).

Shinohara, K., Regan, D., Corrion, A. et al. “Deeply-scaled self-aligned-gate GaN DH-HEMTs with ultrahigh cutoff frequency.” In Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 19.1.1–19.1.4 (2011).

Uren, M. J., Nash, K. J, Balmer, R. S. et al. “Punch-through in short-channel AlGaN/GaN HFETs.” IEEE Transactions on Electron Devices, 53, 395–398 (2006).CrossRef Google Scholar

Park, P. S. & Rajan, S., “Simulation of short-channel effects in N- and Ga-polar AlGaN/GaN HEMTs.” IEEE Transactions on Electron Devices, 58, 704–708 (2011).CrossRef Google Scholar

Jin, R., Song, Y., Ji, M., Xu, H., Kang, J., Han, R., & Liu, X., “Characteristics of sub-100nm ferroelectric field effect transistor with high-k buffer layer.” In Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on, pp. 888–891 (2008).

Terabe, K., Hasegawa, T., Nakayama, T., & Aono, M., “Quantized conductance atomic switch.” Nature, 433, 47–50 (2005).CrossRef Google Scholar PubMed

Thomson, A. F., Melville, D. O. S., & Blaikie, R. J., “Nanometre-scale electrochemical switches fabricated using a plasma-based sulphidation technique.” In Nanoscience and Nanotechnology, 2006. ICONN ’06. International Conference on (2006).

Sakamoto, T., Banno, N., Iguchi, N. et al. “A Ta2O5 solid-electrolyte switch with improved reliability.” In VLSI Technology, 2007 IEEE Symposium on, pp. 38–39 (2007).

Sakamoto, T., Banno, N., Iguchi, N. et al. “Three terminal solid-electrolyte nanometer switch.” In Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp. 475–478 (2005).

Kaeriyama, S., Sakamoto, T., Sunamura, H. et al. “A nonvolatile programmable solid electrolyte nanometer switch.” IEEE Journal of Solid-State Circuits, 40(1), 168–176 (2005).CrossRef Google Scholar

Savio, A., Monfray, S., Charbuillet, C., & Skotnicki, T., “On the limitations of silicon for I-MOS integration.” IEEE Transactions on Electron Devices, 56, 1110–1117 (2009).CrossRef Google Scholar

Shen, C., Lin, J.-Q., Toh, E.-H. et al. “On the performance limit of impact-ionization transistors.” In Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp. 117–120 (2007).

Nagavarapu, V., Jhaveri, R., & Woo, J. C. S., “The tunnel source (PNPN) n-MOSFET: a novel high performance transistor.” IEEE Transactions on Electron Devices, 55, 1013–1019 (2008).CrossRef Google Scholar

Kim, S. H., Agarwal, S., Jacobson, Z. A., Matheu, P., Hu, C., & Liu, T.-J. K., “Tunnel field effect transistor with raised germanium source.” IEEE Electron Device Letters, 31, 1107–1109 (2010).CrossRef Google Scholar

Vega, R. A. & Liu, T.-J. K., “A comparative study of dopant-segregated Schottky and raised source/drain double-gate MOSFETs.” IEEE Transactions on Electron Devices, 55, 2665–2677 (2008).CrossRef Google Scholar

Vega, R. A., Liu, K., & Liu, T.-J. K., “Dopant-segregated Schottky source/drain double-gate MOSFET design in the direct source-to-drain tunneling regime.” IEEE Transactions on Electron Devices, 56, 2016–2026 (2009).CrossRef Google Scholar

Spencer, M., Chen, F., Wang, C. C. et al. “Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications.” IEEE Journal of Solid-State Circuits 46, 308–320 (2011).CrossRef Google Scholar

Chen, F., Kam, H., Markovic, D., Liu, T.-J. K., Stojanovic, V., & Alon, E., “Integrated circuit design with NEM relays.” In Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, pp. 750–757 (2008).

Lee, D., Osabe, T., & Liu, T.-J. K., “Scaling limitations for flexural beams used in electromechanical devices.” IEEE Transactions on Electron Devices, 56, 688–691 (2009).CrossRef Google Scholar

Shen, X., Chong, S., Lee, D., Parsa, R., Howe, R. T., & Wong, H.-S. P., “2D analytical model for the study of NEM relay device scaling.” In Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pp. 243–246 (2011).

Pott, V., Kam, H., Nathanael, R., Jeon, J., Alon, E., & Liu, T.-J. K., “Mechanical computing redux: relays for integrated circuit applications.” Proceedings of the IEEE, 98, 2076–2094 (2010).CrossRef Google Scholar

Joshi, V., Khieu, C., Smith, C. G. et al. “A CMOS compatible back end MEMS switch for logic functions.” In Interconnect Technology Conference (IITC), 2010 International, pp. 1–3 (2010).

Kam, H., Pott, V.,, Nathanael, R., Jeon, J., Alon, E., & Liu, T.-J. K., “Design and reliability of a micro-relay technology for zero-standby-power digital logic applications.” In Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1–4 (2009).

Dadgour, H., Cassell, A. M., & Banerjee, K., “Scaling and variability analysis of CNT-based NEMS devices and circuits with implications for process design.” In Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pp. 1–4 (2008).

Gomez, L., Aberg, I., & Hoyt, J. L., “Electron transport in strained-silicon directly on insulator ultrathin-body n-MOSFETs with body thickness ranging from 2 to 25 nm.” IEEE Electron Device Letters, 28, 285–287 (2007).CrossRef Google Scholar

Vasileska, D. & Ahmed, S. S., “Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation.” IEEE Transactions on Electron Devices, 52, 227–236 (2005).CrossRef Google Scholar

McDaid, L. J., Hall, S., Mellor, P. H., Eccleston, W., & Alderman, J. C., “Physical origin of negative differential resistance in SOI transistors.” Electronics Letters, 25, 827–828 (1989).CrossRef Google Scholar

Fiegna, C., Yang, Y., Sangiorgi, E., & O’Neill, A. G., “Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation.” IEEE Transactions on Electron Devices, 55, 233–244 (2008).CrossRef Google Scholar

Ren, Z., Mehta, S., Cai, J. et al. “Assessment of fully-depleted planar CMOS for low power complex circuit operation.” In Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 15.5.1–15.5.4 (2011).

Liu, Q., Yagishita, A., Loubet, N. et al. “Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond.” In VLSI Technology (VLSIT), 2010 Symposium on, pp. 61–62 (2010).

Andrieu, F., Weber, O., Mazurier, J. et al. “Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20nm low power CMOS and beyond.” In VLSI Technology (VLSIT), 2010 Symposium on, pp. 57–58 (2010).

Bangsaruntip, S., Cohen, G. M., Majumdar, A. et al. “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling.” In Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1–4 (2009).

Yeo, K. H., Suk, S. D., Li, M. et al. “Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires.” In Election Devices Meeting, 2006. IEDM 2006. IEEE International, pp. 1–4 (2006).

Fang, W. W., Singh, N., Bera, L. K. et al. “Vertically stacked SiGe nanowire array channel CMOS transistors.” IEEE Electron Device Letters, 28 211–213 (2007).CrossRef Google Scholar

Dupre, C., Hubert, A., Becu, S. et al. “15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET.” In Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pp. 1–4 (2008).

Singh, N., Lim, F. Y., Fang, W. W et al. “Ultra-narrow silicon nanowire gate-all-around CMOS devices: impact of diameter, channel-orientation and low temperature on device performance.” In Electron Devices Meeting, 2006. IEDM ’06. International, pp. 1–4 (2006).

Kotlyar, R., Obradovic, B., Matagne, P., Stettler, M., & Giles, M. D., “Assessment of room-temperature phonon-limited mobility in gated silicon nanowires.” Applied Physics Letters, 84, 5270–5272 (2004).CrossRef Google Scholar

Ford, A. C., Ho, J. C., Chueh, Y.-L. et al. “Diameter-dependent electron mobility of InAs nanowires.” Nano Letters, 9, 360–365 (2009).CrossRef Google Scholar PubMed

Kuhn, K.J.,, Avci, U.,, Cappellani, A. et al. “The ultimate CMOS device and beyond.” In Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 171–174 (2012).

Colinge, J. P.,, Lee, C. W., Afzalian, A. et al. “SOI gated resistor: CMOS without junctions.” In SOI Conference, 2009 IEEE International, pp. 1–2 (2009).

Colinge, J.-P., Lee, C.-W., Ferain, I. et al. “Reduced electric field in junctionless transistors.” Applied Physics Letters, 96 (2010), .CrossRef Google Scholar

Lee, C.-W., Afzalian, A., Akhavan, N. D., Yan, R., Ferain, I., & Colinge, J.-P., “Junctionless multigate field-effect transistor.” Applied Physics Letters, 94 (2009), .Google Scholar

Cui, Y., Zhong, Z., Wang, D., Wang, W. U., & Lieber, C. M., “High Performance silicon nanowire field effect transistors.” Nano Letters, 3, 149–152 (2003).CrossRef Google Scholar

Rios, R., Cappellani, A., Armstrong, M. et al. “Comparison of junctionless and conventional trigate transistors with down to 26 nm.” IEEE Electron Device Letters, 32, 1170–1172 (2011).CrossRef Google Scholar

Lee, C.-W., Borne, A., Ferain, I. et al. “High-temperature performance of silicon junctionless MOSFETs.” IEEE Transactions on Electron Devices, 57, 620–625 (2010).CrossRef Google Scholar

Choi, S.-J., Moon, D.-I., Kim, S., Duarte, J. P., & Choi, Y.-K., “Sensitivity of threshold voltage to nanowire width variation in junctionless transistors.” IEEE Electron Device Letters, 32, 125–127 (2011).CrossRef Google Scholar

Varadarajan, V., Yasuda, Y., Balasubramanian, S., & Liu, T.-J. K., “WireFET technology for 3-D integrated circuits.” In Electron Devices Meeting, 2006. IEDM ’06. International, pp. 1–4 (2006).

Subramanian, V. & Saraswat, K. C., “Laterally crystallized polysilicon TFTs using patterned light absorption masks.” In Device Research Conference Digest, 1997. 5th, pp. 54–55 (1997).

Subramanian, V., Toita, M., Ibrahim, N. R., Souri, S. J., & Saraswat, K. C., “Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications.” IEEE Electron Device Letters, 20, 341–343 (1999).CrossRef Google Scholar

Oh, J. H., Kang, D. H., Park, M. K., & Jang, J., “Low off-state drain current poly-Si TFT with Ni-mediated crystallization of ultrathin a-Si.” Electrochemical and Solid-State Letters, 12, J29–J32 (2009).CrossRef Google Scholar

Jung, S.-M., Jang, J., Cho, W. et al. “The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 (stacked single-crystal Si) cell, 0.16μm2, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM.” In VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on, pp. 228–229 (2004).

International Technology Roadmap for Semiconductors (ITRS) (2011). Available at: .

Zhirnov, V. V., Cavin, R. K., Hutchby, J. A., & Bourianoff, G. I., “Limits to binary logic switch scaling – a gedanken model.” Proceedings of the IEEE, 91(11), 1934–1939 (2003).CrossRef Google Scholar

Bernstein, K., Cavin, R. K., Porod, W., Seabaugh, A., & Welser, J., “Device and architecture outlook for beyond-CMOS switches.” Proceedings of the IEEE, 98, 2169–2184 (2010).CrossRef Google Scholar

Nikonov, D. E. & Young, I. A., “Overview of beyond-CMOS devices and a uniform methodology for their benchmarking.” Proceedings of the IEEE, 101(12), 2498–2533 (2013).CrossRef Google Scholar

Seabaugh, A. C., & Zhang, Q., “Low-voltage tunnel transistors for beyond CMOS logic.” Proceedings of the IEEE, 98, 2095–2110 (2010).CrossRef Google Scholar

Vandenberghe, W. G., Soree, B., Magnus, W., Groeseneken, G., & Fischetti, M. V., “Impact of field-induced quantum confinement in tunneling field-effect devices.” Applied Physics Letters, 98 (2011), .CrossRef Google Scholar

Haran, B. S., Kumar, A., Adam, L. et al. “22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell.” In Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pp. 1–4 (2008).

Kim, D.-H., & del Alamo, J. A., “30 nm E-mode InAs PHEMTs for THz and future logic applications.” In Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pp. 1–4 (2008).

Salvatore, G. A., Bouvet, D., & Ionescu, A. M., “Demonstration of subthrehold swing smaller than 60 mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack.” In Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pp. 1–4 (2008).

Sakamoto, T., Iguchi, N., & Aono, M., “Nonvolatile triode switch using electrochemical reaction in copper sulfide.” Applied Physics Letters, 96, (2010), .CrossRef Google Scholar

Dewey, G., Chu-Kung, B., Boardman, J. et al. “Fabrication, characterization, and physics of III-V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing.” In Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 33.6.1–33.6.4 (2011).

Majumdar, A., Ren, Z., Koester, S. J., & Haensch, W., “Undoped-body extremely thin SOI MOSFETs with back gates.” IEEE Transactions on Electron Devices, 56, 2270–2276 (2009).CrossRef Google Scholar

Auth, C., Allen, C., Blattner, A. et al., “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors.” In VLSI Technology (VLSIT), 2012 Symposium on, pp. 131–132 (2012).

Colinge, J.-P., Lee, C.-W., Afzalian, A. et al. “Nanowire transistors without junctions.” Nature Nanotechnology, 5(15), 225–229 (2010).CrossRef Google Scholar PubMed