6 - SystemVerilog and Vera in a verification flow

Summary

Introduction

The goal of this chapter is to illustrate the practical applicability of the simulation-based validation concepts in the book by applying them to a design example. We will use both System Verilog [1] and Vera [2] as hardware-verification languages (HVLs) in which we will implement the entire validation framework for the design example. Simulation is the most widely used technique for verification of design models. The design to be verified is described in a hardware-description language (HDL) and is referred to as the design under verification (DUV). This provides an executable model or models of the DUV. These models could be developed at different levels of abstraction.

A high-level design specification is then analyzed to produce stimulus or input test vectors. The input test vectors are applied to the models. The inputs are propagated through the model by a simulator and finally the outputs are generated. A monitor is used to check the output of the DUV against expected outputs for each input test vector. It is constructed based on an interpretation of the expected design behavior from the specification. If there is any observed deviation from the expected output, a design error is considered to have been found, and debugging tools are used to trace back and diagnose the source of the problem. The problem usually arises from either incorrectly modeled design or incorrectly modeled timing. Once the problem source is identified, it is fixed and the new model is simulated. In an ideal world, the model should be tested for all possible scenarios.