5 - Architectures of Parallel Computers

Summary

Classification of Architectures

Roughly speaking, computer architecture is a structure of computer system components. Architecture, in addition to manufacturing technology, is a major factor determining the speed of a computer. Therefore designers devote a great deal of attention to improving computer architectures. One of architecture classifications is Flynn's taxonomy, which is based on the concepts of instruction stream and data stream. An instruction stream is a sequence of instructions executed by a processor, and a data stream is a sequence of data processed by an instruction stream. Depending on the multiplicity of instruction and data streams occurring on a computer, Flynn has distinguished four classes of architectures (Figure 5.1).

Computers of SISD architecture, in brief SISD computers, are conventional computers wherein a processor executes a single instruction stream processing a single data stream. In modern processors, regularly more than one instruction is executed within a single clock cycle. Processors are equipped with a certain number of functional units enabling implementation of instruction in a pipelined fashion. Processors with multiple functional units are called superscalar.

Suppose that the process of executing an instruction consists of six sequentially performed microoperations (also termed microinstructions): fetch instruction (FI), decode instruction (DI), calculate operand address (CA), fetch operand (FO), execute instruction (EI), write result (WR). A sequence of microoperations making up the process of implementing an instruction is called pipeline. Each microoperation in the sequence is also called stage of a pipeline, so in our example we have the 6-stage pipeline. Assume that the separate functional units (hardware circuitry) J₁, J₂, …, J₆ have been implemented in a processor to perform particular microoperations. Pipelined execution of an instruction stream i₁, i₂, …, i₈, … is illustrated in Figure 5.2. In the first stage (clock cycle 1), unit J₁ fetches instruction i₁ from program memory and forwards it to unit J₂ for decoding. In the second stage (clock cycle 2) unit J₂ decodes instruction i₁, and unit J₁ fetches instruction i₂. At the end of stage 2, units J₁ and J₂ send results of their operation to units J₂ and J₃, respectively, and so on.