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from Part X - 802.11 Hardware Design
Published online by Cambridge University Press: 10 December 2009
A single-chip IEEE 802.11g compliant wireless LAN system-on-a-chip (SoC) that implements all RF, analog, digital PHY and MAC functions has been integrated in a 0.18-µm CMOS technology. The IC transmits 0 dBm EVM-compliant output power for a 64 QAM OFDM signal. The overall receiver sensitivities are better than -92 dBm and - 73 dBm for data rates of 6 Mbps and 54 Mbps, respectively.
Introduction
The IEEE 802.11g specification which was only ratified in June 2003, has become the most widely deployed wireless local area network (WLAN) standard today. Its popularity is due in large part to its support for higher data rates while maintaining backwards compatibility to legacy IEEE 802.11b WLANs. An IEEE 802.11g device achieves the higher data rate when communicating with other 802.11g devices by using orthogonal frequency division multiplexing (OFDM) modulation. When communicating with legacy 802.11b devices, it will revert back to either direct sequence spread spectrum (DSSS) or complementary code keying (CCK) modulation. The standard uses 83.5-MHz of available spectrum in the 2.4-GHz band and allows for three non-overlapping channels. The data rates range from 1-2 Mbps using DSSS modulation, 5.5-11 Mbps using CCK modulation, and 6-54 Mbps using OFDM modulation. As in the IEEE 802.11a specification the OFDM in 802.11g uses 52 sub-carriers, each of which can be modulated with BPSK, QPSK, 16-QAM or 64-QAM.
The rapid adoption of IEEE 802.11g WLANs and their growing popularity in portable applications such as PDAs and cellphones highlighted the need for a low-cost, small form factor solution.
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