A - The VeSPA instruction set architecture (ISA)

Summary

The instruction set architecture (ISA) of the VeSPA (Very Small Processor Architecture) defines the interface between the hardware designer and the assembly language programmer. It consists of all of the programmer accessible storage, plus all of the instructions.

Notational conventions

The following notation is used in this appendix to describe the ISA.

• #. This symbol is used to identify an immediate operand.

• rdst. One of the general-purpose registers that will be used as the destination to store the result produced by an instruction.

• rs1, rs2. One of the general-purpose registers that will be used as a source value in an operation.

• rst. The register that will be written to memory in a store operation.

• R[rx]. The contents of general-purpose register rx.

• Mem[x]. The contents of memory location x.

• immedX. An X-bit immediate value used as a literal.

• LABEL. Used in the assembler to symbolically specify a memory location, that is, by name.

• ;. Used in the assembler to mark the beginning of a comment.

• sext(x). Sign-extend the value x by replicating the sign bit as many times as necessary to extend x to a 32-bit value.

• setcc(x). Set the condition code bits according to the value x.

Storage elements

The following storage elements are defined in the ISA and are accessible to the assembly language programmer, either directly or indirectly as a side effect of some instructions.

• Memory. The main memory consists of 232 locations, each of which is eight-bits wide. The memory uses a big-endian organization so that the most-significant byte of a 32-bit value is stored at the smaller memory address.

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