Appendix 1.2 - Building multi-transistor logic gates

Summary

In Chapter 1, we described the three basic logic gates used to build computers. Here we will illustrate a combination gate – a NAND built with MOSFETs. As shown in Figure A-1.2.1, it takes three transistors of the same n-channel type in this configuration. A CMOS configuration for the same gate function requires four transistors.

The NAND is a combination of an AND gate and an inverter. The top MOSFET is connected to a voltage source of 10 volts which biases it in the on (conducting) state.

The truth table gives the logical combinations of this gate.

If both voltage A and voltage B are positive (1), then the bottom two transistors are turned on and hence conducting. This effectively connects the current flow from the voltage source through the top transistor to ground, and the output voltage V is 0. Hence it takes two positive (1) inputs to produce a (0) output.

On the other hand, if either of the two voltages at A or B is 0, then the current path is connected to the output, resulting in 10 volts at the terminal, which is defined as a “1.”