Engineered non-wetting surfaces inspired by biological species are of interest in the industry due to their potential applications such as water repelling, self-cleaning, anti-icing, anti-corrosion, anti-fouling, and low fluid drag surfaces. However, the adoption of non-wetting surfaces in large scale industrial applications has been hampered by synthesis techniques that are not easily scalable and the limited long term stability and wear robustness of these surfaces in service. In this study, we demonstrate a simple, low cost, and scalable electrochemical technique to produce robust composite coatings with tunable non-wetting properties. The composite coatings are composed of an ultra-fine grain nickel matrix with embedded hydrophobic cerium oxide ceramic particles. Comprehensive characterization, including wetting property measurements, electron microscopy, focused ion beam analysis, hardness measurements, and abrasive wear testing were performed to establish the structure-property relationships for these materials. The grain refinement of the nickel matrix contributes to the high hardness of the composites. As a result of the bimodal CeO2 particle size, hierarchical roughness is present on the surface of the composite, leading to remarkable non-wetting properties, even after 720 m of abrasive wear.

Knowledge of the composition of many cultural heritage objects is limited, resulting in many unanswered questions in regards to the provenance, composition, and production methods. In this paper, our objective is to show that dual beam scanning electron microscope (SEM) and focused ion beam (FIB) can be used rapidly and non-destructively to determine the surface and bulk metal compositions in small cultural heritage objects. We show, for the first time, that this novel FIB technique can be successfully applied non-destructively to cultural heritage objects by examining three representative silver plated objects (Candelabra, “Century” spoon, and New York World’s Fair spoon) from the Dallas Museum of Art’s unparalleled collection of modern American silver. In each case, we successfully reveal and characterize the bulk metal as well as the Ag-plating, up to ∼80 µm deep and show that there is no visual damage resulting from the milling process of the FIB. This novel characterization technique can be applied, due to its ease of availability and rapid use, to many other problems in addition to silver plated objects, making dual beam SEM/FIB a possible cornerstone technique in the study of cultural heritage objects.

This paper describes an alternate two-step metallization scheme for porous dielectrics. The patterned dielectric surface is first treated in a plasma etch chamber where the dielectric surface is coated with a very thin carbon-based film. This is followed by electroless copper deposition. The plasma post-etch treatment (PET) film seals the pores of the dielectric, minimizes dielectric damage, and functionalizes the dielectric to enable electroless plating.

The motivation of this study is to provide answers to questions rising with 3D stacking of semiconductor chips. This includes the development and validation of concepts for 1) Through Silicon Via (TSV) formation, 2) metal layer build-up, 3) various types of assembly and packaging concepts and methods, as well as 4) process characterization.

The investigations discussed here have been conducted on test wafer (ATEC2) developed by Fraunhofer IZM-ASSID. This design contains dedicated test structures which have been implemented to enable different unit processes and allows easy physical analysis. One of those test structures has been used to study the impact of the TSV density on the stress generation after TSV fill, anneal and CMP (chemical mechanical planarization) including copper protrusion and planarization behaviour. First results of the interaction between different TSV plating bath chemicals, anneal procedures and wafer bow obtained using test wafer ATEC1 were already presented during ICPT 2011.

The process flow applied in this investigation was (1) TSV filling by electro-plating, (2) anneal, and (3) CMP. Physical analysis including inline metrology has been conducted between all process steps.

The test wafers processed were divided into two groups according to the utilized copper plating bath chemistries. The copper TSV metallization was carried out by electro-chemical deposition in plating bath chemicals from two different suppliers. 3D microscope inspection was conducted for surface analysis. After TSV filling the copper surface shows protrusion on top of the TSVs and ring-shaped non-uniformities around the filled TSV. These structures were analysed after each step of the process flow.

An anneal process was conducted after TSV plating. The annealing temperature was varied to investigate its influence on the material properties (protrusion caused by copper recrystallization) and the dip behaviour. The experiments were accomplished at 250 degree Celsius and above.

Afterwards all test samples were processed by CMP with different selective slurries and analysed by AFM (atomic force microscopy) and optical methods. Bow and warpage measurements of the test wafers taken after each process step have been analysed.

Our investigation has demonstrated the influence of the additives on the behaviour of different plating bath chemistries during temperature treatment (copper recrystallization) and therefore also the planarization behaviour after CMP.

We report the novel use of semiconductor photocatalysis for the deposition of metal onto insulating surfaces and the in-process formation of nano-structured porosity within this metal. In the process of Photocatalytically Initiated Electroless Deposition (PIED) we have developed a controllable, spatially selective and versatile metallisation technique with several advantages over traditional, non-photocatalytic techniques such as enhanced controllability and purity of the deposit as well as reduced operational costs and environmental impact. With the addition of a self-assembled, hexagonally close-packed microparticle template to the substrate prior to metal deposition, PIED can be used to fabricate thin metal films with highly ordered porosity on the nano-scale. Nanoporous metallisation in this way is able to produce substrates with potentially wide applications such as membrane and separation technology, energy storage and sensors – especially surface enhanced resonance Raman spectroscopy (SERRS).

During the excavations made at a burial of the post-Classic Mayan period (1220-1521 A.D.) in the pyramid number 2 of the pre-Hispanic site of Lagartero, Chiapas, Mexico, a set of four small metallic artifacts depicting reptile’s heads, were recovered. The objects were in poor conservation conditions and were taken to the Metal Conservation Laboratory of the National School of Conservation (ENCRyM- INAH) for suitable cleaning and conservation treatments.

Analyses allowed identifying important technological features such as gilding remains. The analytical techniques included optical microscopy followed by X-Ray Fluorescence Spectroscopy (XRF), and Scanning Electron Microscope-coupled with Energy Dispersive Spectrometer (MEB-EDS). For the elemental depth profile a combined Particle X-Ray Emission Spectroscopy and Rutherford Backscattering Spectrometry (PIXE–RBS) analysis was carried out.

The results indicate that the objects are made of a copper alloy, and then gilded probably using electrochemical replacement gilding (thickness has less than 1 μm). This technology has been observed in other metallic objects recovered from the Chichen-Itza Cenote in Yucatan, but it was not available in Mesoamerican areas so far. So, it could imply that these artifacts might have been imported from South American areas.

Silicon carbide is a semiconductor with desirable material properties, such as a wide bandgap and high thermal conductivity. It is an excellent material for constructing power switching devices operating in harsh environments where conventional semiconductors cannot adequately perform. One example of such a power device is a bipolar junction transistor (BJT). While the potential of the SiC BJT is recognized, appropriate techniques for producing devices is lacking due to its difficulty.

For example, in order to achieve a high voltage 4H-SiC BJT switch with nanosecond switching time, the device must have a low base resistance. The simulation results indicate that for an emitter width of 2.0 μm and a base width of 1.2 μm the distance between the two should be 0.4 μm or less to meet the requirement for base resistance. To produce the above-described geometries and spacing, it is desirable to construct the device in a self-aligned manner. Self-alignment in this context means that the relative spacing of features of the device, such as contacts, is automatically controlled by the processing sequence and process parameters, rather than by the careful alignment prior to exposure of a photo sensitive layer. For this purpose, we developed a novel self-aligned process for SiC BJT devices, that enables the fabrication of the design with high yield, as standard silicon self-aligned technique are not applicable.

The newly developed process starts with the deposition of the emitter contact metal, which provides the metal mask for the etching of the emitter ridges. Next, the wafer is planarized with photoresist and etched, so that only the emitter contacts are exposed. Electroless plating is then used to enlarge the contacts, and after removal of the resist, the plating provides an overhang, suitable for lift-off of the base contact metal. After the base contact metal deposition, the structure is planarized and etched, this time with a silicon dioxide layer, again exposing the plated emitter contacts and the lift-off step is the wet etching of the plated metal. The emitters are then all connected with a blanket wiring level, which also forms the base contact pad. This process is simpler and more robust than the process we developed to date. The main difference is the inclusion of a sacrificial lift-off overhang, created by electroless plating. It enables a well controlled overhang independent of steepness of the SiC ridge profile and the height of the emitter mesa. We successfully fabricated the overhang structure on 4H-SiC substrates.

In conclusion, we report the demonstration of a new self-aligned process, which provides a self-aligned emitter contact, a self-aligned base contact and eliminates the need for via holes smaller than the emitter stripe widths. We consider this new process a major improvement over existing processes to fabricate SiC BJT devices.

In 3D packaging, Through Silicon Vias (TSVs) with high aspect ratios and depths measuring tens of microns are filled by advanced Cu electroplating processes. Today's 300mm TSV plating platforms are intended to produce bottom-up via fill, no seam voids, and minimal, controlled overburden. To achieve this, the preceding Cu-seed coverage must be continuous at a constant resistance, and the plating chemistries optimized. However, other factors such as hardware configurations and simple depletion of the plating formulations during the extended TSV process can lead to high Cu overburden thickness requiring a high removal rate (HRR) chemical-mechanical polish (CMP) process to remove the thick Cu layer.

Presented here are CMP results of a thick Cu overburden (~6um) resulting from the fill of 5 x 25um TSVs on 300mm wafers. The goal is to uniformly polish the overburden and utilize the tool's endpoint system at Cu clear before the next step of conventional barrier CMP. Slurries were screened for removal rate, uniformity, planarization ability, and defectivity. This study focuses on achieving a removal rate of >2.5um/min through evaluation of several commercial slurries in a multi-step polish application. Cross-sections post-plating show the Cu overburden, barrier and liner layer. Cross-sections post-CMP quantify Cu recess, dielectric loss, and presence/absence of seam defects. The process selected is demonstrated to achieve good planarization results with low occurrence of polish defects, at a rate and selectivity suitable for emerging 3D TSV Cu CMP applications.

This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.

This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.

In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.

This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

Ionic Polymer Metal Composites (IPMCs) are manufactured by electroless deposition of metal on Nafion. This deposition method results in the IPMCs with thickness between 0.17mm to 0.20mm with the electrode thickness of around a few m each. It is now generally accepted that on mechanical deformation IPMC produces charge thus making these materials potentially suitable for energy harvesting applications. Due to thin metal plating and inherited flexibility of the Nafion film the IPMCs suffer in stiffness that may be required for some energy harvesting applications. Also earlier works have shown that 0.20mm thick IPMC produce better battery charging than 0.17mm thick one. Hot pressing, using metal mold, Nafion films was employed to produce thicker and comparatively stiffer IPMCs electroded with Palladium metal. Palladium was used because of shorter manufacturing time. This IPMC shows improved energy harvesting. Due to the increased thickness these IPMCs also function as better capacitors than their conventional counterparts. On application of voltage, these IPMCs show charging and discharging effects of a capacitor. This property of IPMC may be useful for storing charge.

Pd-Ni-P films were systematically plated using a mixture of Pd and Ni-P plating solutions. The films were plated by electroless alloy plating using three Pd/Ni-P mixture ratios (1/1, 3/1, and 1/3) at plating temperatures adjusted within a range from 303 to 333K. An increase in the Ni-P mixture ratio or in the plating temperature led to an increase in the Ni content of the plated film and a decrease in the Pd content. The P content of the plated film remained almost constant. These results indicate that the composition of the fabricated film can be effectively controlled by adjusting the plating temperature and mixture ratio. The plated film had a flat surface morphology without defects such as pinholes or nodules. TEM observation of the film revealed an amorphous structure. DSC analysis during heating revealed an endothermic peak and exothermic peak corresponding to the glass transition and crystallization, respectively. On the basis of these results, we concluded that the plated Pd-Ni-P film was metallic glass. The plated Pd-Ni-P film was also confirmed to have catalytic activity, as the Ni-P alloy was plated directly onto the film without catalyzation by electroless plating. The high flatness and uniformity of the surface of the Ni-P film plated onto the Pd-Ni-P film suggests that the Ni-P film grew via a one-dimensional growth mechanism.

This paper proposes a novel coating method combining supercritical fluid technology and electroless plating in a hybrid technique. The electroless plating reactions are carried out in an emulsion of supercritical carbon dioxide (sc-CO2) and an electroless plating solution with surfactants. The Ni-P film obtained by this proposed technique was a uniform and conformal film without the pinholes and nodules. The Ni-P film fabricated by our technique was smoother and more uniform than the substrate after pretreatment and the conventional electroless plating.

Ag particles were generated on Ag+-doped polyimide film by ion exchanging, followed by copper deposition using metallic silver particles as seeds. The Cu layers were coated on the surface of polyimide films by electroless plating method. The surface image and morphology of Cu layers on the polyimide films were characterized with scanning electron microscopy (SEM), and atomic force microscopy (AFM). The chemical composition on the PI film was investigated energy dispersive X-ray (EDX) spectrometer.

Intermetallic compound (IMC) spalling from electroless Ni-P film was investigated with lead-free solders in terms of solder-deposition methods (electroplating, solder paste, and thin foil), P content in the Ni-P film (4.6, 9, and 13 wt% P), and solder thickness (120 versus .200 μm). The reaction of Ni-P with Sn3.5Ag paste easily led to IMC spalling after 2-min reflow at 250 °C while IMCs adhered to the Ni-P layer after 10-min reflow with electroplated Sn or Sn3.5Ag. It has been shown that not only the solder composition but also the deposition method is important for IMC spalling from the Ni-P layer. The spalling increased with P content as well as with solder volume. Ni3Sn4 intermetallics formed as a needle-shaped morphology at an early stage and changed into a chunk-shape. Needle-shaped compounds exhibited a higher propensity for spalling than chunk-shaped compounds because many channels among the needle-shaped IMCs facilitated Sn penetration. A reaction between the penetrated Sn and the Ni3P layer formed a Ni3SnP layer and Ni3Sn4 IMCs spalled off the Ni3SnP surface. Dewetting of solder from the Ni3SnP layer, however, did not occur even after spalling of most IMCs.

Growth of Trypanosoma cruzi as colonies on solid medium has not been widely used as an experimental procedure. We therefore sought to establish a reliable and routine plating method. The optimal results were achieved with a matrix of 0·65% low melting point agarose onto which epimasigotes from the mid-to-late logarithmic phase of growth were spread. Colonies could be isolated after incubation for 21 days in a humidified 5% CO2 environment at 28°C. Plating efficiencies in the range of 40% were obtained by this method and clones could be recovered into liquid medium or onto blood-agar slopes with a high success rate. The procedure has also been adapted for the isolation of genetically transformed clones after electroporation of epimastigotes with either plasmid or cosmid vectors. This was best achieved by inclusion of the electroporated cell inoculum in a 0·6% agarose overlay containing G418 as the selective drug, on top of a 0·8% agar base. Transformation efficiencies were as high as 10−5 cells per μg of DNA. A reliable plating method for T. cruzi will have many applications and is a significant step towards the use of ‘shotgun transformation’ to generate libraries of T. cruzi recombinants.