Doherty power amplifier output networks with maximized bandwidth

Abstract

A method is presented to optimize the combining network and the post-matching network of a Doherty power amplifier (DPA) for maximizing the bandwidth. For widely applicable results, RF power transistors are approximated in the large-signal regime using a simple analytical model with a few parameters. A definition of bandwidth of DPA is given, which involves gain and efficiency at full-power and 6 dB backoff. Different combining network topologies are compared in terms of this bandwidth definition. The element values are optimized using two factors, one to scale the combining node impedance and the other to scale the impedance seen by the transistors. For each optimized topology, explicit formulas are given resulting in the element values in terms of the optimized values and a few transistor parameters. The method presented also leads to a proper selection of the post-matching network.

1. Introduction

Modern wireless communication systems use high peak to average power ratio (PAPR) signals to utilize spectrum efficiently with high data rates [1]. Such signals cause power amplifiers to operate with a reduced efficiency [2]. Doherty power amplifier (DPA), first proposed by Doherty [3] and well discussed in [4] provides an efficient amplification for signals having high PAPR.

There has been a lot of work on increasing the efficiency of the DPA or increasing the frequency range where the DPA is efficient. Efficiency optimizations can be achieved in narrowband applications, but in broadband applications, it is not trivial to achieve similar performance. Using more efficient amplifier modes such as class-E or class-F enables efficient operation controlling harmonic terminations in backoff of narrowband applications [5, 6]. In [7] tuned load and class-F are compared at the output of the DPA using benefits of GaN-HEMT transistors. There are also asymmetrical DPA approaches [8] where the backoff peaking is set to 8.0–9.9 dB.

When it comes to building a wideband DPA, there are several limitation factors which are summarized and categorized in [9]. The most notable ones are the device output capacitance and the frequency response limitation of λ/4 impedance inverters. In [10], a DPA is built over the frequency range of 1.7–2.3 GHz, focusing more on the device output capacitance and not considering λ/4 impedance inverter's limitation. Parasitic compensation techniques are used to achieve 49% [11] and 87% [12] fractional bandwidths (FBW). Digitally controlled dual-RF input DPAs are also another approach to increase the efficiency bandwidth compared to single input DPAs [13]. In [14], a 100% FBW digital DPA was presented based on Doherty-outphasing continuum and in [15], a 50% FBW digital three-way DPA with backoff reconfigurability is presented.

Frequency analysis of the DPA is extensively investigated in [16] exploiting the bottleneck on the limitation of impedance inverter's frequency response. By modifying the impedance transformation ratio of transmission lines, the impedance seen by the carrier amplifier has less variation over the frequency and the efficiency bandwidth is increased up to an octave [17]. The impedance inverter's limitation is more dominant if the device output capacitance is small, such as in GaN devices, with which FBW = 25% is achieved by a modified load modulation network [18]. Adoption of broadband post matching networks instead of quarter-wave inverters are proposed to achieve FBW of 43% [19], 53% [20], and 70.7% [21].

The use of a two-section matching circuit at the peaking amplifier enhances the efficiency bandwidth [22]. It is also possible to achieve wide bandwidth with LDMOS transistor using two section transmission line matching where [23] presents 52% FBW with 280W output power. In [24] a closed-form design technique is presented on how to implement input, output splitting/combining networks and demonstrating 83% FBW. Biasing transistors with a constant current source rather than a voltage source results in FBW of 93.3% [25].

In this paper, we determine the topology and element values of optimized output network of a DPA, for the purpose of maximizing the bandwidth. Instead of using specific and complex vendor models of transistors, we use a simple generic and robust transistor model to make the results more general. In section “Theory”, we introduce our analytical transistor model that is used in approximating the behavior of any RF power amplifier including DPA. We divide the output network into two parts: a combining network and a post-matching network. We present different combining network topologies in section “Output network” and introduce two factors for the purpose of bandwidth optimization. Section “Optimized combining networks” introduces the definition of bandwidth of the DPA dependent both on gain and efficiency at full-power and 6 dB backoff. There, we provide explicit formulas for the bandwidth maximized values of combining network element values that are dependent on the optimized factors and the transistor parameters. A post-matching network not causing a bandwidth reduction can be selected subsequently. In section “Example designs”, we give examples to demonstrate the use of the method, where all element values are calculated using the presented formulas. The resultant output networks are also analyzed using a harmonic balance simulator using vendor models of transistors to show that the results are close enough. The values can be used as a good starting point for further optimization using harmonic balance with more accurate models of transistors. Section “Experimental results” presents experimental results verifying the validity of the method.

2. Theory

2.1 Large-signal intrinsic RF transistor model

The drain current of the RF transistor is assumed to depend linearly on the gate voltage, v _GS, minus the threshold voltage, V _T, through the transconductance of G _m. We note that this is a good approximation for the popular GaN transistors. We write the instantaneous intrinsic drain current, i _D, in terms of the drain to source voltage, v _DS, as

(1)$$i_D = \left\{\matrix{G_m( v_{GS}-V_T) \, f( v_{DS}) \hfill & \rm{if } v_{GS}\ge V_T \hfill \cr 0 \hfill & \rm{otherwise} \hfill \cr \hfill }\right.$$

with

(2)$$f( v_{DS}) = 1-{1\over 2}\left(1-{{v}_{DS}\over V_{DD}}\right)^{N_e}-{1\over 2}\left(1-{v_{DS}\over V_{DD}}\right)^{N_e + 1}$$

where f() is continuous function for all v _DS values and N _e is an even integer showing the order of knee function approximation. The resultant I − V characteristics of our model is shown in Fig. 1 for N _e=14.

Fig. 1. I-V characteristics of our model with N _e = 14.

This function is an improved version of that introduced recently [26]. Unlike the model there, our transistor characteristics are never in the fourth quadrant and hence it always remains a passive device. Therefore, our model is usable for transistors under any class of operation experiencing any complex or negative real-part loads. This is especially important for DPA analysis since the individual transistors of a DPA may experience very high-Q or even negative real-part loads under certain conditions. It is found that harmonic balance simulation of DPA using vendor models of transistors causes convergence problems under certain combining network combinations making an optimization very difficult.

The knee voltage, V _K, is defined as the point where the the slope of f(v _DS) with respect to v _DS/V _DD is unity. For a given V _K and V _DD, the most appropriate even integer, N _e, can be determined from the solution of

(3)$$N_e\left(1-{{V}_{K}\over V_{DD}}\right)^{N_e-1} + ( N_e + 1) \left(1-{V_{K}\over V_{DD}}\right)^{N_e} = 2$$

2.2 Analysis of a simple RF power amplifier using the model

The analysis method can be explained using an RF power amplifier shown in Fig. 2. The transistor is assumed to have a voltage-independent drain capacitance of C and a series package inductance of L _s. The amplifier operates with a supply voltage of V _DD.

Fig. 2. Schematic of an RF power amplifier.

The transistor input is excited with a sinusoidal signal at ω shifted with a bias voltage V _B. To simplify the analysis, we assume that all harmonic voltages are shorted at the intrinsic transistor drain. This is a good approximation if the package inductance L _s is small and the inductance, L, forms a resonant circuit at fundamental frequency shorting the harmonics. Hence the drain voltage is assumed to be purely sinusoidal, and we can write v _DS as:

(4)$${v}_{DS}( \theta) = V_{DD} + {V}_1\cos( \theta + \phi) $$

An input voltage of v _GS = V _B + V _incosθ results in a drain current of

(5)$$\eqalign{i_D& = A( \theta) \left[1-{1\over 2}\left({V_1\over V_{DD}}\right)^{N_e}\cos^{N_e}( \theta + \phi) \right.\cr & \quad\left. + {1\over 2}\left({V_1\over V_{DD}} \right)^{N_e + 1}\cos^{N_e + 1}( \theta + \phi) \right]}$$

with

(6)$$A( \theta) = \left\{\matrix{G_m( V_{in}\cos\theta + V_B-V_T) \hfill & \rm{if } \cos\theta> -{V_B-V_{T}\over V_{in}} \hfill \cr 0 \hfill & \hbox{otherwise} \hfill \cr \hfill }\right.$$

Following the approach of [26], we expand (5) as the product of an infinite series with a finite series. Hence one can obtain the DC current, I ₀, and the fundamental current, I₁ (in the phasor form), both as a finite series. Note that I ₀ and I₁ depend on N _e, V _in, V _B − V _T, and the phasor V₁ = V ₁e ^jϕ, in a nonlinear manner through the functions f ₁ and f ₂ defined as

(7)$$\eqalign{I_0& = f_1( N,\; V_{in},\; V_B-V_T,\; {\bf {V}_1}) \cr & = A_0k_0 + {1\over 2}\sum_{n = 1}^{N_e + 1}A_{n}k_{n, R}\cr {\bf {I}_1}& = f_2( N,\; V_{in},\; V_B-V_T,\; {\bf {V}_1}) \cr & = A_1k_0 + {1\over 2}A_0k_{1, R} + {1\over 2}\sum_{n = 1}^{N_e + 1}\left[( A_{n-1} + A_{n + 1}) k_{n, R}\right. }$$

(8)$$\quad\left. + j( A_{n-1}-A_{n + 1}) k_{n, Q}) \right]$$

where A _n, k _n,R, and k _n,Q are defined in Appendix A. We should also satisfy V₁ = Z _TI₁ or

(9)$${\bf {V}_1} = {Z}_Tf_2( N,\; V_{in},\; V_B-V_T,\; {\bf {V}_1}) $$

where Z _T = V₁/I₁ is the drain impedance seen by the transistor. This value is easily found as a function of ω in terms of Z _out and ABDC parameters of the network composed of C, L _s, and L.

(10)$${Z}_T = {A{Z}_{out} + B\over C{Z}_{out} + D}$$

With a given ω, N, V _DD, V _in, and V _B − V _T, we solve¹ the nonlinear equation of (9) to find V₁. Once the complex valued quantity, V₁, is found, we can determine I ₀ from (7), and the output RF power, P _out, using

(11)$${P}_{out} = {1\over 2}{\cal R}e\left\{{Z}_{out}\right\}\vert {\bf {I}_2}\vert ^2\rm{ \, with \, }{\bf {I}_2} = {\bf {V}_1\over A{Z}_{out} + B}$$

The efficiency is determined from

(12)$$\eta = {{P}_{out}\over {I}_0V_{DD}}$$

2.3 RF power amplifier examples

As the active device we choose Cree CGH40010 GaN transistor to build a power amplifier with V _DD = 28 V. We model the transistor using the parameters G _m = 0.66 A/V, V _T = −3.3 V, C = 1.84 pF and L _s = 0.26 nH, and N _e = 14. Here, G _m and V _T are determined from the transistor's I-V characteristics. C and L _s are estimated from the vendor specified optimal load impedance. N _e is found from the knee voltage using (3).

We first bias the transistor in Class-B (V _B = V _T) and choose L = ∞. Figure 3 shows the calculated power and efficiency load-pull contours using our model at 2.5 GHz as Z _out is varied. The full-power load-pull contours are generated with an input drive level to reach the rated power at the corresponding optimum load. At the same load, we reduce the input power to reach a 6 dB lower output power to define the 6 dB back-off (BO) level. Then the load-pull contours are regenerated at this BO level.

Fig. 3. Power (left, in 1 dB steps) and efficiency (right, in 5% steps) load-pull contours of Class-B transistor at 2.5 GHz on 50 Ω Smith charts at two-input levels: full-power (solid) and 6 dB BO (dashed).

We repeated the load-pull simulation (Fig. 4) for the same amplifier with transistor biased as Class-C. It is excited with twice the input RF voltage to obtain the same output power with a properly selected gate bias voltage.

Fig. 4. Figure 3 repeated for Class C transistor at full-power (solid) and at 5 dB BO (dashed) rather than at 6 dB BO.

The maximum power is achieved nearly at the same impedance value as the Class-B amplifier. As BO is increased the optimal values move toward higher impedances more rapidly compared to Class-B amplifier.

To verify the accuracy of our model, we present comparison of our results for Class-B and Class-C amplifiers with harmonic balance simulation² at 2.5 GHz using vendor supplied nonlinear model in Table 1. The results of our model are reasonably close to the results of more accurate vendor model.

Table 1. Comparison of harmonic balance and our model for Class-B and Class-C amplifiers at full-power (FP) and 6 dB output BO

Table 2 lists our model's optimal load impedance, Z _opt, defined at the drain pin (D in Fig. 2) of the transistor package for different frequencies. With a suitable value of shunt inductance (L of Fig. 2), it is possible to move the center of load-pull contours to the real axis to find the optimal load resistance, R _opt, which is also defined at the drain pin of the transistor. At low frequencies, R _opt is equal to the optimal load resistance (26.6 Ω) of the intrinsic transistor, since the effects of the drain capacitance, C and the package inductance, L _s, are negligible.

Table 2. Optimal load impedance (Z _opt), and load resistance (R _opt, used with a shunt tuning inductor, L) for CGH40010 GaN transistor at full-power

Note that this simple model of the transistor can be scaled by a factor ξ to wider gate width transistors of the same family: For a transistor with ξ times gate width³, the parameters above become ξG _m, ξC, L _s/ξ, L/ξ, R _opt/ξ, Z _out/ξ, while V _T and η remain unchanged. Hence the load pull contours of Figs 3 and 4 are applicable if the reference impedance of the Smith chart is set to (50/ξ) ~Ω. For example, for CGH40025 and CGH40045 power transistors, we need to set ξ = 2.5 and 4.5, respectively.

2.4 Analysis of Doherty power amplifier

We consider the generic DPA shown in Fig. 5 composed of carrier and peaking amplifiers, using the Class-B and Class-C amplifiers identical to those described in the previous section.

Fig. 5. Schematic of the generic DPA.

The desired combining node impedance of Z _L is obtained using a post-matching network of sufficient bandwidth. The carrier transistor is biased as Class-B (V _Bc = V _T), while the peaking transistor is biased as Class-C with V _Bp. The combining network with two branches should provide the desired impedances to the transistor drains. When both transistors are driven at full-power, the impedances presented to both drains should nearly⁴ be equal to R _opt. At 6 dB BO, the peaking transistor is off. Its output capacitance, C, should be tuned out at the center frequency to prevent loading to the combining node. At the same BO level, the combining network should present a load of 2R _opt to the carrier transistor drain, to achieve the desired high efficiency. For an efficiency peak at 6 dB BO, we set β = 2α, where α and β are the input power divider ratios as indicated in Fig. 5. For a lossless divider we have α ² + β ² = 1 and hence $\alpha = 1/\sqrt {5} {,\; } \beta = 2/\sqrt {5}$. We introduce a proper phase shift at the input of the carrier amplifier to equalize the phases at the combining node.

Referring to Fig. 5, the output loads of transistors including their parasitic capacitances and matching networks can be represented as a function of ω with ABCD parameters having complex entries. The combining node is terminated with the impedance Z _L having a voltage phasor of V_L at ω.

Let the carrier and peaking transistors’ voltage and current phasors at ω be denoted by V_c, I_c, V_p, and I_p, respectively. From ABCD matrices shown in Fig. 5, we have:

(13)$${\bf {V}_c} = A_c{\bf {V}_L} + B_c{\bf {I}_{Lc}}$$

(14)$${\bf {I}_c} = C_c{\bf {V}_L} + D_c{\bf {I}_{Lc}}$$

(15)$${\bf {V}_p} = A_p{\bf {V}_L} + B_p{\bf {I}_{Lp}}$$

(16)$${\bf {I}_p} = C_p{\bf {V}_L} + D_p{\bf {I}_{Lp}}$$

The voltage at the combining node is given by

(17)$${\bf {V}_L} = ( {\bf {I}_{Lc}} + {\bf {I}_{Lp}}) {Z}_L$$

Substituting equation (17) in equations (14), (16) and solving for I_Lc and I_Lp, we rewrite equation (17) as

(18)$${\bf {V}_L} = {Z}_L{D_p{\bf {I}_c} + D_c{\bf {I}_p}\over D_cD_p + ( C_cD_p + C_pD_c) {Z}_L}$$

Substituting I_Lc, I_Lp and equation (18) into equations (13) and (15), we get

(19)$$\eqalign{{\bf {V}_c}& = { B_cD_p + ( A_cD_p + B_cC_p) {Z}_L\over D_cD_p + ( C_cD_p + C_pD_c ) {Z}_L}{\bf {I}_c}\cr & \quad + {( A_cD_c-B_cC_c) {Z}_L\over D_cD_p + ( C_cD_p + C_pD_c ) {Z}_L}{\bf {I}_p} \triangleq {Z}_c {\bf {I}_c}\cr {\bf {V}_p} & = { B_pD_c + ( A_pD_c + B_pC_c) {Z}_L\over D_cD_p + ( C_cD_p + C_pD_c ) {Z}_L}{\bf {I}_p} }$$

(20)$$\quad + {( A_pD_p-B_pC_p) {Z}_L\over D_cD_p + ( C_cD_p + C_pD_c ) {Z}_L}{\bf {I}_c}\triangleq {Z}_p{\bf {I}_p}$$

where Z _c and Z _p are defined as the impedances seen by each transistor.

As in the case of stand-alone amplifier, we can write I_c and I_p as the fundamental component of clipped cosine waves:

(21)$${\bf {I}_c} = f_2( N,\; \alpha V_{in},\; V_{Bc}-V_T,\; {\bf {V}_c}) $$

(22)$${\bf {I}_p} = f_2( N,\; \beta V_{in},\; V_{Bp}-V_T,\; {\bf {V}_p}) $$

Substituting equations 21 and 22 into equations 19 and 20, we get two nonlinear equations with two unknowns: V_c and V_p. These equations can be solved simultaneously to find the unknown values. We can then proceed to find the supply currents of carrier (I _0c) and peaking (I _0p) amplifiers from

(23)$${I}_{0c} = f_1( N,\; \alpha V_{in},\; V_{Bc}-V_T,\; {\bf {V}_c}) $$

(24)$${I}_{0p} = f_1( N,\; \beta V_{in},\; V_{Bp}-V_T,\; {\bf {V}_p}) $$

The phasor at the combining node, V_L, is found using equations (18), (21), and (22). Hence the output power is written as

(25)$$P_{out} = {1\over 2}{\cal R}e\left\{{\vert {\bf {V}_L}\vert ^2\over {Z}_L}\right\}$$

and the efficiency can be found from

(26)$$\eta = {P_{out}\over V_{DD}( {I}_{0c} + {I}_{0p}) }$$

3. Output network

The output network plays a crucial role in the performance of the DPA [16]. We divide the output network into two parts: A combining network (CN) which combines the outputs of both amplifiers and a post-matching network (PMN), which transforms the combining node impedance to the load impedance. In this section, we present different CN and PMN topologies.

3.1 Combining network (CN)

We introduce two factors for the purpose of bandwidth optimization. Using the first factor, ζ, we set the combining node impedance at center frequency, ω ₀, as

(27)$$Z_L( \omega_0) = {\zeta}{R_{opt}\over 2}$$

Using the second factor, κ, we set Z _c and Z _p at full-drive as

(28)$$Z_c( \omega_0) = Z_p( \omega_0) = \kappa R_{opt}$$

and at 6 dB BO (Z _cBO) as

(29)$$Z_{cBO}( \omega_0) = 2\kappa R_{opt}$$

At the center frequency and full-power, the impedance transformation circuits at the output of both transistors should transform Z _c(ω₀) = Z _p(ω₀) = κR _opt to 2Z _L so that when they are connected in parallel at the combining node it becomes Z _L. This corresponds to a transformation ratio of ζ/κ. At 6 dB BO, the carrier amplifier's impedance transformation circuit should transform Z _cBO(ω₀) = 2κR _opt to Z _L, corresponding to a transformation ratio of ζ/4κ.

With a selection of κ < 1, the small-signal gain and maximum power are reduced at the center frequency, while increasing the performance at band edges, contributing to the bandwidth enhancement. However, we will keep 0.84 < κ < 1.2 to prevent a gain reduction of more than 1.5 dB and to preserve the linearity within acceptable limits.

3.1.1 Conventional CN

The conventional combining network is shown in Fig. 6.

Fig. 6. Conventional combining network.

The output capacitance, C, of each transistor is tuned out at the center frequency with a suitable shunt inductance, L, as given in Table 2, acting also like the drain bias RFC. If L turns out to be too small for practical realization, it can be replaced by a high impedance (Z _H) transmission line with a length x (in λ₀ units) of

(30)$$x = {1\over 2\pi}\tan^{-1}\left({\omega_0L\over Z_H}\right)$$

with a slight degradation in bandwidth performance.

Since the peaking transistor is connected directly to the combining node, it is not possible to optimize ζ and κ independently. To maintain the equal contribution of power at full-drive we must set

(31)$$\zeta = \kappa \, \rm{ and } \,Z = \zeta R_{opt}$$

Obviously, the delay compensation at the input side depicted in Fig. 5 must be swapped between transistors for proper operation.

3.1.2 CN type I

The CN [22, 24] shown in Fig. 7 achieves the desired characteristics using three quarter-wave transmission lines, which allows easy implementation, especially at high frequencies. Z ₁ should transform 2Z _L = ζR _opt to κR _opt at full power and Z _L = ζR _opt/2 to 2κR _opt at 6 dB BO. Similarly, Z ₂ and Z ₃ should transform ζR _opt to κR _opt at the full-drive level. When the peaking transistor is off, no loading is presented at the combining node at the center frequency since there is a shunt inductance, L, to tune-out the drain capacitance, C, at that frequency. Since C is tuned out only at the center frequency, its loading at other frequencies is one of the bandwidth limiting factors.

Fig. 7. CN I.

The transmission line impedances are given by

(32)$$Z_1 = \sqrt{\kappa\zeta} R_{opt}$$

(33)$$Z_2 = \kappa^{3/4}\zeta^{1/4} R_{opt} \quad Z_3 = \kappa^{1/4}\zeta^{3/4} R_{opt}$$

Note that both Z ₂ and Z ₃ contribute to transformation for a wider band operation.

3.1.3 CN type II

A wide-band combining network using lumped elements [19, 27] is shown in Fig. 8. The inverters connected to the drain of the transistors have the possibility of absorbing the drain capacitance, C, and the package inductance, L _s, as part of the inverter, resulting in a higher bandwidth.

Fig. 8. CN type II.

For the carrier amplifier, we need an inverter that transforms ζR _opt to κR _opt under full-power. The same inverter will transform ζR _opt/2 to 2κR _opt with 6 dB BO.

The peaking amplifier needs an identical inverter. Since the drain capacitor of the transistor is already present, depending on the value of the inverter ratio, adding a shunt capacitance or inductance on the drain side may be necessary. The component values can be calculated as:

(34)$$C_1 = {1\over \omega_0 R_{opt}\sqrt{\zeta\kappa}}\quad L_1 = {R_{opt}\sqrt{\zeta\kappa}\over \omega_0}-L_s$$

(35)$$C_5 = {1\over \omega_0 R_{opt}\zeta}\quad L_5 = {R_{opt}\zeta\over \omega_0}$$

where L _s is the series package inductance at the drain.

(36)$$\eqalign{C_{2}& = \left\{\matrix{ C_{1}-C \hfill & \rm{if } \, C_{1}> C \hfill \cr 0 \hfill & \hbox{otherwise} \hfill }\right.}$$

(37)$$\eqalign{L_2& = \left\{\matrix{ 1/[ ( C-C_{1}) \omega_0^2] \hfill & \rm{if }C_{1}< C \hfill \cr \infty \hfill & \hbox{otherwise} \hfill }\right.}$$

For a good bandwidth performance, it is important to choose ζ and κ so that C ₁ is nearly equal to the drain capacitance, C, if possible. In that case, there is no need for C ₂ while a large value of L ₂ can be kept to bias the device.

3.1.4 CN type III

The inductor, L ₁, of the inverter of CN type II, can be replaced by a transmission line [12], making the circuits easily realizable at microwave frequencies (see Fig. 9). It can be approximated using a transmission line of impedance Z _H and length x ₃ (in λ₀ units) as seen in Fig. 9.

Fig. 9. CN III.

We choose Z _H to be 40% higher than the higher impedance value to shorten its length, but not too high to avoid fabrication problems. The two unknown values, x ₃ and C ₃, can be found by equating the input impedance of the inverter to the required impedance at the center frequency.

The required values are determined by solving a number of cases and fitting a polynomial to the results. For an inverter that inverts R ₀=ζR _opt to rR ₀ with r=κ/ζ <1, we have

(38)$$\eqalign{\omega_0 C_3& = {-171.67 r^3 + 466.58 r^2 -505.32 r + 279.58\over 100R_0}\cr x_3& = {25.15 p^3-67.43 p^2 + 141.99 p + 26.97\over 1000}}$$

(39)$$\quad\rm{with } \,\, Z_H = 1.4R_0$$

where

(40)$$p = \left(\sqrt{r}-{\omega_0L_s\over R_0}\right)^2$$

If Z _H value of equation (39) is too high for implementation, equations (63) and (64) of Appendix B can be used for a smaller Z _H. If the required shunt capacitance is smaller than the drain capacitance of the transistor, a shunt inductance (L ₃) can be added, which can also act like the DC power feed for the transistor. The remaining component values can be determined from

(41)$$ \hskip -2.7pc \eqalign{C_{4}& = \left\{\matrix{ C_{3}-C \hfill & \rm{if } C_{3}> C \hfill \cr 0 \hfill & \rm{otherwise} \hfill }\right.}$$

(42)$$\eqalign{L_{3}& = \left\{\matrix{ 1/[ ( C-C_{3}) \omega_0^2] \hfill & \rm{if }C_{3}< C \hfill \cr \infty \hfill & \rm{otherwise} \hfill }\right.}$$

(43)$$ \hskip -8.6pc \eqalign{Z_5 = \zeta R_{opt}}$$

3.2 PMN

A PMN providing the desired combining node impedance can be chosen depending on the bandwidth requirement and the ratio of Z _out to Z _L. A number of possibilities are shown in Fig. 10.

Fig. 10. Different PMNs.

In (a), a single quarter-wave transmission line is used to transform Z _L to Z _out with

(44)$$Z_A = \sqrt{Z_LZ_{out}}$$

If ζR _optc/2 is close to Z _out, one section is enough even in a wide band. For a larger transformation ratio, two λ/4 transmission lines may be used as shown in (b) with values

(45)$$Z_B = Z_L^{3/4}Z_{out}^{1/4} \, {\rm and } \, {\rm Z}_C = {\rm Z}_L^{1/4} {Z_{out}^{3/4}}$$

The impedance transformation can also be achieved with a small size lumped element inverter shown in (c). In this case, we should choose

(46)$$L_a = {\sqrt{Z_LZ_{out}}\over \omega_0} \, {\rm and } \, {C}_a = {1\over {\omega}_0^2L_a}$$

For a wider bandwidth or when the transformation ratio is high, two inverters can be used as shown in (d) with

(47)$$L_b = {{Z_L^{3/4}Z_{out}^{1/4}}\over \omega_0} \, {\rm and } \, C_b = {1\over \omega_0^2L_a}$$

(48)$$L_c = {{Z_L^{1/4}Z_{out}^{3/4}}\over \omega_0} \, {\rm and } \, C_c = {1\over \omega_0^2L_a}$$

When a lumped inductance is not desirable or practical, PMN shown in (e) can be utilized: a high impedance (Z _K) transmission line and two shunt capacitors, C _A and C _B. Since we do not need an inverter, the shunt capacitances do not have to be equal in value, hence providing higher bandwidth. The electrical length, y ₁, of the transmission line (in λ₀ units) can be found from the solution of the nonlinear equation

(49)$${Z_A\over Z_K}-{2\pi y_1\over \cos^2( 2\pi y_1) } = 0$$

We equate the real part of Z _L1 to Z _L(ω ₀) and the imaginary part of Z _L1 to 0, both at ω ₀. We find C _A and C _B, by solving the resulting nonlinear equations numerically. For an impedance transformer that transforms rR ₀ to R ₀ with 0.4 < r < 1 we have

(50)$$\omega_0C_A = {27.06r^3-76.17r^2 + 83.14r-11.76\over 100R_0}$$

(51)$$\eqalign{\omega_0C_B& = {-181.59r^3 + 503.13r^2-568.26r + 268.09\over 100R_0}\cr y_1& = {25.37r^3-78.17r^2 + 108.17r + 29.24\over 1000}}$$

(52)$$\quad\rm{and } \, Z_K = 1.4R_0$$

Since the combining networks are of low-pass type, the band center is smaller than ω ₀.

For a wider band or when the transformation ratio from Z _L to Z _out is high, one may repeat the transformation operation in two steps and use two sections of the circuit of (e) as shown in (f).

The performances of different PMNs as a function of transformation ratio, Z _out/Z _L, are given in Table 3 for the condition that the transformed impedance has a return loss higher than 15 dB. Note that the networks can also be used with the inverted transformation ratio.

Table 3. Bandwidth performance of different PMNs

An inspection of the table indicates that lumped element networks (PMN types (c) or (d)) can be used only when the transformation ratio and/or the bandwidth is small. For wider bandwidths or when the transformation ratio is high, for example, with high power transistors with large ξ values, PMN type (b) gives the best performance. PMN types (e) and (f) give a good performance despite their smaller size. The center frequency of the PMN may have to be shifted, since the band limits are not always symmetrical.

4. Optimized combining networks

For the purpose of optimization, we define the bandwidth of a DPA in which all of the following constraints are satisfied:

• • The efficiency at 6 dB output BO is higher than 50%

• • The efficiency at full-power is higher than 60%

• • The power at 6 dB output BO is at most 1.5 dB less than the normal value.

• • The power at full-power is at most 1.5 dB less than the normal value.

Here, “full-power” is defined as the   dB gain compression point at the center frequency with the optimal load. We should also consider linearity of the DPA and keep it within acceptable limits. The 1.5 dB value above is chosen as a compromise between linearity and bandwidth. A higher value will result in a higher bandwidth with more nonlinearity.

For bandwidth optimization of the conventional CN, the combining node impedance, Z _L = ζR _opt/2 should be as high as possible to minimize the quality factor of drain capacitance tuning network. We can increase ζ only up to 1.2, since ζ = κ > 1.2 results in an unacceptable level of nonlinearity.

For other types of CN, we can increase ζ to higher values, while keeping κ less than unity for a large band.

As an example, we consider CN type I and PMN type (a) with ζ = 4.8, κ = 0.84 at f ₀ = 3.5 GHz. We show the power and efficiency contours defined by the constraints above on the Smith charts of Fig. 11 for both carrier and peaking amplifiers. In the same charts, we also show the impedances experienced by the carrier (Z _c) and peaking (Z _p) amplifiers as a function of frequency at two drive levels, which should stay inside the relevant contours.

Fig. 11. Limiting power (left) and efficiency (right) contours on Smith charts, for carrier amplifier at full-power (solid) and 6 dB backoff (dotted), and for peaking amplifier at full-power (dashed). Impedances seen by the amplifiers as a function of frequency (0.79f ₀ to 1.20f ₀) are also shown.

These Smith charts can be used to observe the variation of impedances as the values of ζ and κ are varied. The values are then optimized to reach the widest bandwidth. Those factors should be chosen to keep the impedance values within the power and efficiency contours for as wide frequency range as possible. We note that decreasing the value of κ moves the impedance curves toward the left, reducing the power and efficiency at the center frequency while boosting power and efficiency at the band edges. On the other hand, a higher ζ improves the bandwidth at the backoff level resulting in a reduction of the bandwidth at full-power.

Table 4 gives the optimized results for CGH400XX series transistors at different center frequencies assuming that PMN matches Z _L to Z _out perfectly at all frequencies. The values of ζ and κ as well as the normalized band limits are given in the same table for different types of combining networks.⁵ This table is applicable for transistors scaled with factor ξ, since an increase in the transistor gate width simply causes a reduction of the combining node impedance to Z _L/ξ.

Table 4. Normalized band limits of DPA with optimized ζ and κ for CGH400XX family transistors at different frequencies

The input matching network and PMN is assumed to be properly chosen not causing a band limitation.

The effect of series drain inductance, L _s, is negligible at lower frequencies or in MMIC circuits where the transistors are integrated with the rest of the combining circuit. In such cases, it is possible to list more general results in terms of drain quality factor, Q, rather than frequency. With the definition

(53)$$Q = {\omega_0 C}{R_{opt}}$$

we provide such results in Table 5. Since all values in the table are normalized, they are applicable for the design of a DPA at any frequency band with any transistor, if C and R _opt of transistor are known.

Table 5. Normalized band limits of DPA with optimized ζ and κ for a transistor with L _s=0 and different combining networks

The input matching network and PMN are assumed not to cause a band limitation.

Inspection of Tables 4 and 5 indicates that widest bandwidth is obtained with CN type II or III since C and L _s can be absorbed as part of the combining network. In Fig. 12 we present a comparison of different CN types for CGH400XX transistors with f ₀ = 2.5 GHz, showing the power and efficiency at full-power and 6-dB BO. CN type III gives the widest bandwidth, while type II is slightly worse. CN type I may still be preferred for its ease of implementation even though it has the smallest bandwidth.

Fig. 12. Comparison of power outputs (left) and efficiencies (right) of CN types I (red), II (blue), and III (green), all using transistors with Q = 0.77. Solid lines represent full power and dashed lines represent 6 dB BO.

Tables are given for our specific bandwidth definition given above. If the limiting values in that definition are relaxed, it is possible to obtain DPAs with a wider bandwidth but with a lower performance.

5. Example designs

To demonstrate the use of our method, we give a number of example DPA designs.

5.1 Example I

As the first example, we use a CN type I with CGH40010 (ξ=1) at f ₀ = 3.5 GHz. At this frequency we have R _opt = 16.4 Ω and L = 0.935 nH from Table 2. From Table 4, we set ζ = 4.8 and κ = 0.84 to get a band from f ₁ = 2.8 GHz to f ₂ = 4.16 GHz. With Z _out/Z _L = 1.27, it is sufficient to use PMN type (a), (c), or (e) without limiting the bandwidth. The values of components in the output network as calculated from relevant equations are given in Table 6 for PMN type (a).

Table 6. Component values for the CN type I and PMN type (a) with f ₀ = 3.5 GHz

Note that the inductance L can be replaced with a high impedance transmission line of length determined by equation (30). The results from both our model and harmonic balance simulation using vendor supplied nonlinear model of the transistors are shown in Fig. 13. Since we ignore the bandwidth limitation of the input matching networks, for a fair comparison we connect voltage sources with zero source impedance as the input driving sources in the harmonic balance simulations. Similarity between the curves is a verification for our simple model.

Fig. 13. Power output (left) and efficiency (right) of the the first example as a function of frequency for full-power (red) and for 6 dB BO (blue). Harmonic balance simulations (dashed) are also drawn.

In Fig. 14 we present the calculated AM-AM and AM-PM distortions of this example at different frequencies. The phase distortion becomes significant when the peaking transistor begins to conduct. As it is previously shown [28–31], frequency-dependent AM/PM nonlinearity is an undesired attribute of Doherty amplifiers, which may be reduced by analog or digital predistortion methods or by modifying the input power split ratio.

Fig. 14. AM-AM (left) and AM-PM (right) characteristics of the first example at 3.1, 3.3, 3.5, 3.7, and 3.9 GHz.

If we had used the transistor CGH40045 with ξ = 4.5, L, Z ₁, Z ₂, and Z ₃ would have been scaled down by 4.5 and Z _out/Z _L = 1.27 ξ = 5.71 would have required PMN type (b) or (f). For such a large transistor, however, the assumption of input side matching network not limiting the bandwidth may be optimistic.

5.2 Example II

As the second example, we use CN type II with CGH40025 (ξ = 2.5) for f ₀ = 2.5 GHz. We use R _opt = 26.6/ξ = 10.6 Ω from Table 2 since the effect of L _s is eliminated with CN type II. From Table 4, we set ζ = 3.1 and κ = 0.87 and get a band from f ₁ = 1.60 GHz to f ₂ = 2.95 GHz. With Z _out/Z _L = 1.30 ξ = 3.03, we should use PMN type (b) or type (f) not to reduce bandwidth. The component values are given in Table 7 for PMN type (b).

Table 7. Component values of the second example of CN type II and PMN type (b) at f ₀ = 2.5 GHz

We plot the results in Fig. 15 along with harmonic balance simulation of the same circuit.

Fig. 15. Power output (left) and efficiency (right) of the second example as a function of frequency for full-power (red) and for 6 dB BO (blue). Harmonic balance simulations are also shown (dashed).

5.3 Example III

At the last example, we use a small center frequency (f ₀ = 0.5 GHz) to demonstrate the use of Table 5. At this frequency the effect of L _s is negligible. With R _opt = 26.6 Ω and C = 1.84 pF, we have Q = 0.15. We use CN type III. From the table we set ζ=3.0 and κ = 0.97 to get a band from f ₁ = 0.26 to f ₂ = 0.61 GHz. With Z _out/Z _L = 1.25 a PMN type (e) is sufficient. The component values are given in Table 8.

Table 8. Component values of the example III at f ₀ = 0.50 GHz

6. Experimental results

For the purpose of comparing our results with experimental results, we relax the efficiency limits in our bandwidth definition to take care of losses in the output combining network: 46% for 6 dB BO and 56% for full-power.

6.1 DPA with type I combining network

We built a DPA using type I CN with ζ = 4.8 and κ = 0.84 centered at 1.0 GHz. The schematic of the amplifier using two CGH40010 transistors is given in Fig. 16. Since Z _out/Z _L = 0.80, a simple PMN of a tapered line of 0.35 λ at 1.0 GHz is sufficient. Optimized element values along with calculated values are given in Table 9.

Fig. 16. The circuit schematic of fabricated wideband Doherty power amplifier.

Table 9. Component values for CN type I and OMN type (a) at f ₀ = 1.0 GHz

The DPA is implemented on Rogers 4003C⁶ substrate with 0.508 mm thickness. The photo of the implementation can be seen in Fig. 17. The performance of the amplifier is depicted in Fig. 18 where the efficiency is better than 56% at full power and 46% at 6 dB BO. We achieved a bandwidth from 0.67 to 1.35 GHz, while the predicted bandwidth from Table 4 is 0.69–1.30 GHz, verifying our method.

Fig. 17. Photograph of the fabricated wideband DPA. The dimensions are 20 × 10 cm.

Fig. 18. Measurements of fabricated DPA: power output (left) and efficiency (right) as a function of frequency for full-power (red) and for 6 dB BO (blue).

6.2 Examples from previous works

We chose three experimental studies from literature whose limiting values are within or close to those in our bandwidth definition. Table 10 lists those studies for the estimated ζ and κ values to the best of our understanding as well as the predicted and measured band limits. Comparison of ζ and κ values to those in the Table 4 indicates that they are close to optimum values. The measured band limits are also consistent with our expectations. It is possible to find other examples in the literature with a wider bandwidth, but they have lower performance for efficiency within the band.

Table 9. Summary of this work (T.W.) and three studies from the literature at full-power (FP) and at 6 dB BO

7. Conclusion

In this paper, we presented a method to design the output combining network of a wideband DPA maximizing the bandwidth of operation. We used a simple analytical model of the RF transistor with a few parameters (V _T, G _m, N _e, C, and L _s), and showed that the results are very similar to those obtained from harmonic balance simulation with a much more complex model of transistor.

We first presented a bandwidth definition for the DPA with strict limits on efficiency and power output performance. To optimize the bandwidth performance, we introduced two factors, ζ and κ. They are the multiplying factors for the impedance at the combining node and the impedance seen by transistors, both defined at the center frequency. For the given three parameters of a transistor and the type of the combining network, an optimal pair of ζ and κ can be determined. We presented a table that lists those values as a function of frequency. We also gave explicit formulas for all element values of the combining network. We showed that the higher power transistors of the same family can be used by a proper scaling of the combining network element values. We also presented a method to choose the post-matching network in order not to degrade the bandwidth performance.

If the package inductance, L _s, of the transistor is negligible, then it is possible to list the optimal values only in terms of transistor output quality factor, Q, making this second table more general for applications in lower frequencies or in MMICs.

The tables can be used to determine the potential bandwidth performance of a DPA using transistors with a quality factor, Q. Alternatively, they can be used in choosing a proper transistor for a DPA with a given bandwidth goal. We gave example designs to demonstrate the use of both tables to find all element values.

Among the three different CN topologies studied, type II gives a good bandwidth performance in applications where the distributed components are not preferred because of their size. CN type III can be implemented easily at higher frequencies and with a slightly better performance compared to type II. CN type I should be preferred for its robustness if a wide bandwidth is not required and the size is not a problem.

A higher power version of the DPA with the same bandwidth can be implemented by scaling of the transistors and the combining network element values, provided that a sufficiently wideband post-matching network is utilized to take care of the reduced combining node impedance.

Obviously, for the complete DPA design input matching, stabilization and input unequal dividing network must be added. Due to the bandwidth limitation of the input side, the resulting bandwidth of the DPA will be somewhat smaller than predicted here.

Even though our transistor model is extremely simple, the results obtained from our model are very close to harmonic balance simulations using the complex nonlinear models of transistors. Hence our method is very useful if there is no available nonlinear model of the transistors in a MMIC application. One can easily extract R _opt, C, and L _s from the measured load-pull data of the transistor. Those parameters are sufficient to design the output combining networks.

If the transistor has a vendor supplied model, the proposed circuit topology and calculated values from our method can be used as a good starting point of further optimization in a harmonic balance simulator.