Interface decohesion is increasingly becoming a reliability concern in multilayer interconnect structures. It is therefore necessary to provide adhesion tests as a part of materials characterization procedures and to study the fundamental material properties that affect interface toughness. A sandwich structure 4-point bend test was developed for measuring the adhesion between interlayer dielectric and metal interfaces. This technique offers well defined and easily controllable fracture processes and simple analyses based rigorously on fracture mechanics. Using this technique, a number of interfaces were studied. For conventional interconnect systems consisting of Al lines and SiO2 as the interlayer dielectric, the focus was to improve the interface fracture toughness through structure design and process engineering. Potential low dielectric constant materials, such as polymers and porous SiO2, were also studied as candidates for interlayer dielectric materials in the future. Interface strengthening effects of both mechanical and chemical origin, including interface roughness and thin film plasticity, as well as alteration of chemical bonding were explored.

The strain energy release rates for the converging decohesion crack in a multilayered film on a substrate have been calculated using the finite element method. The results for the energy release rate as a function of the intrinsic stress, the thickness of the superlayer and the modulus ratio will be presented. A simple functional form for the results will be shown. The effects of plasticity of the thin metal layer on the energy release rate have been examined. The results show that the effect of plastic deformation is not significant for the converging decohesion crack. The effects of the line width have also been addressed. The results show that for two-layer films the energy release rate for steady-state decohesion cracks decreases dramatically as B/h decreases, in the range B/h<40, where B is the line width and h is the thickness of the superlayer. For narrow lines the plane strain solutions overestimate the energy release rate. The numerical results are consistent with the experimental observations on lines with different width.

Progressive (or time dependent) debonding of interfaces poses serious problems in interconnect structures involving multilayer thin films stacks. The existence of such subcriticai debonding associated with environmentally assisted crack-growth processes is examined for a TiN/SiO2 interface commonly encountered in interconnect structures. The rate of debond extension is found to be sensitive to the mechanical driving force as well as the interface morphology, chemistry, and yielding of adjacent ductile layers. In order to investigate the effect of interconnect structure, particularly the effect of an adjacent ductile Al-Cu layer, on subcriticai debonding along the TiN/SiO2 interface, a set of samples was prepared with Al-Cu layer thicknesses varying from 0.2–4.0 μm. All other processing conditions remained the same over the entire sample run. Results showed that for a given crack growth velocity, the debond driving force scaled with Al-Cu layer thickness. Normalizing the data by the critical adhesion energy allowed a universal subcriticai debond rate curve to be derived.

As in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic “decohesion” test for measuring interface fracture resistance in integrated circuits.

Nano-indentation testing has been used to quantitatively assess the adhesion of thin copper films, sputtered to thicknesses of 150 nm to 1500 nm. Copper films of low residual stress were deposited via RF diode cathode sputtering onto SiO2/Si substrates. Overlayers of DC magnetron sputtered high residual stress tungsten, 850 nm thick, were additionally used to provide a driving force for delamination. All films tested exhibited buckle-driven delamination, from which the interfacial toughness was estimated to be 0.2 – 2 J/m2, which is comparable to the thermodynamic work of adhesion. The use of an overlayer requires extensions of existing models, but otherwise does not change the interfacial adhesion, allowing measurements of films that would not otherwise delaminate.

Experiments have been performed on soft aluminum films deposited on hard ceramic substrates to explore the influences of interfacial adhesion on mechanical property measurement by nanoindentation. The substrate materials included soda-lime silicate glass, aluminum oxynitride (ALON), and (100) sapphire. Thin films of high purity aluminum were sputtered onto each substrate to a thickness of 500 nm. Because the films were deposited simultaneously, the only major difference in the specimens was the nature of the substrate, which exerts an important influence on film adhesion through interfacial chemistry. Of the substrates examined, aluminum adheres strongly to glass and sapphire, but poorly to ALON. In addition, two different types of aluminum films on sapphire were examined - one with and the other without a 10 nm interlayer of amorphous carbon which significantly reduces film adhesion. Testing revealed important differences in the hardness of the specimens when measured by standard nanoindentation methods. Characterization of the residual hardness impressions by high resolution scanning electron microscopy showed that the hardness differences arise from an influence of interfacial debonding and film delamination on pile-up in the film. Furthermore, when the pile-up is accounted for in contact area determinations, the film hardness is actually independent of the substrate, thus indicating that the hardness differences observed in nanoindentation testing are an artifact of the testing analysis procedure. Results of the experiments are documented and discussed.

The ability to accurately measure the mechanical properties of thin metallic films is important in the semiconductor industry as it relates to device reliability issues. One popular technique for measuring thin film mechanical properties is nanoindentation. This technique has the advantage of being able to measure properties such as hardness and elastic modulus without removing a film from its substrate. However, according to a widely-held rule of thumb, intrinsic film properties can be measured in a manner which is not influenced by the substrate only if the indentation depth is kept to less than 10% of the film thickness, which is often not practical. In this work, a method for making substrate independent hardness measurements of soft metallic films on hard substrates is proposed. The primary issue to be addressed is the substrate-induced enhancement of indentation pile-up and the ways in which this pile-up influences the contact area determined from analyses of nanoindentation load-displacement data. Based on experimental observations of soft aluminum films on silicon, glass, and sapphire substrates, a simple empirical relationship is derived which relates the amount of pile-up to the contact depth. From this relationship, a simple method is developed which allows the intrinsic hardness of the film to be measured by nanoindentation methods even when the indenter penetrates through the film into the substrate.

Quantitative measurement of the adhesion strength of thin film metallizations has been achieved by a novel technique employing electrostatic forces to generate delaminating stresses. This technique has been used in testing the adhesion of Al-Cu, Cu, and Al multilayer films deposited on Si. Micro-blister-type failure is revealed by scanning electron microscopy. The delamination process and the geometry of the blister are discussed. The measured adhesion data fit a Weibull distribution function.

The evolution of thermal stresses in aluminum interconnects, with the presence of local debonded areas between the aluminum line and the surrounding dielectric, is studied numerically. Local interfacial debonding is presumably due to contamination during the line patterning process. Various geometrical features of the interconnect and the debond segment are assumed, and the resulting stress fields are examined by recourse to two- and three-dimensional finite element analyses. Implications of the findings to the interconnect reliability, particularly stress-induced voiding in aluminum lines, are discussed.

Gate dielectrics for advanced ULSI circuits are rapidly scaling below 10 nm. Thinner dielectrics and smaller lateral dimensions are essential to produce high performance transistors for memories, microprocessors and microcontrollers. In this overview we will discuss the factors that affect the performance and reliability of scaled gate dielectrics. Process parameters that affect oxide and oxynitride dielectrics include substrates, pre-gate cleaning, growth parameters and growth techniques as well as oxide and oxynitride dielectric materials. Thin dielectrics require new or modified measurement methods and extensive use of physical analysis techniques such as SIMS, XPS, AFM and TEM to characterize these materials. Boron diffusion through thin gate oxides, HCI stress, and process induced damage can degrade dielectric quality and affect long term reliability. These factors will affect the performance and reliability of circuits with scaled gate dielectrics.

This work describes the development of a new grow-deposit-grow cluster process to grow ultra-thin stacked oxides. Two approaches for stacked oxide synthesis are discussed, namely thermal and chemical stacked oxides. Fabrication of chemical stacked oxide involves forming the first grown layer chemically after pre-gate cleaning, subsequent deposition of a TEOS-SiO2 layer and final densification/oxidation in a single low pressure (LP) furnace operation. In comparison, all three steps for thermal stacked oxide are accomplished by the LP cluster operation. Both processes offer the advantages of reduced cycle time and higher throughput to the stacked gate technology that produces superior Si/SiO2 interfaces and exhibits higher resistance to plasma-damage during ultra large scale integrated circuit (ULSI) processing. The quality and electrical characteristics of the stacked oxides are discussed.

In this study, we present results of both in-situ and ex-situ measurements of stress generated during dry oxidation of silicon. We show that the mechanical stress in as-grown dry oxides is a strong function of oxidation temperature and oxide thickness, but a weak function of oxygen partial pressure. We have identified a structural relaxation phenomenon after the oxide is formed, and found that the viscosity of the oxide increases with its age; consequently, the stress relaxation slows down due to this increase of viscosity. In this paper, we present a one-dimensional mechanical model to simulate the stress generation and relaxation during dry oxidation of silicon. The simulations of both in-situ and ex-situ tests are in good agreement with the experimental measurements.

In this paper the effect of different annealing conditions on boron diffusion is studied for 3 nm gate dielectrics. The use of amorphous material instead of polycrystalline material and the influence of nitridation (two-step N2O oxidation) was investigated. A better control on the flatband voltage (VFB) shift was observed for amorphous-Si gate as compared to polycrystalline-Si gate. A reduction in VFB was observed for N2O oxides as compared to pure oxides, but VFB was still above the ideal value for some of the thermal treatments. A significant reduction in QBD is observed for p+ gates as compared to n+ gates. The lowest post-implantation anneal gives the highest QBD for all the different combinations.

This paper discusses the challenges involved in improving gate oxide reliability for advanced integrated circuits through review of literature and other relevant data. We believe that gate oxide reliability improvements can be engineered by paying special attention to the process conditioning of the top and bottom electrode components of the thin oxide dielectric system in advanced ULSI technologies. We present examples that demonstrate the impact of process and materials on the performance of thin oxide. The data encompasses the effects of substrate, isolation, and top electrodes on gate oxide quality using a variety of methodologies to assess reliability.

This paper addresses two aspects of the chemical bonding arrangements at Si-SiO2 interfaces that impact significantly on electrical performance and reliability of devices with ultrathin gate dielectrics with oxide equivalent thicknesses, toxeq, in the regime of direct tunneling; i.e., toxeq < 3 nm. These are i) minimization of suboxide bonding arrangements that contribute to roughness in an interfacial transition region, and ii) monolayer nitrogen atom incorporation.

We demonstrate that the reliability of ultrathin (< 10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on the position at the substrate for constant current gate injection (Vg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of oxides is closely related to the electric field across the gate oxide, which is influenced by the cathode Fermi level. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field must be higher to give the same injection current density. A higher electric field gives more high energy electrons at the anode, and therefore the damage is more at the substrate interface. Different substrate types cause no effect on the oxide electric field, and as a result, they do not influence the degradation.

The UV-excited chlorine radical treatment effectively removed trace metal contaminants from Si ans SiO2 surfaces. We have found that this is predomonantly attributed to reactions between metal and chlorine, and metal oxides and silicon chloride, respectively. The former process was subjected to identify a breakdown spot on a thin gate dielectric film. After dielectric breakdown, a silicon crystallized filament as small as a few nanometers in diameter was formed and was selectively etched with chlorine radicals revealing a successively-etched region of the Si substrate. Nonuniformi t i es of native oxides on silicon were also detected using the same method. Gettering and etching with a poly Si layer showed a possibility to make a gate dielectric film damage free and contamination free. Densi fication of native oxides formed after conventional wet cleaning of silicon was made with UV-excited oxygen radicals. Electrical characteristics of gate dielectrics treated with UV-excited chlorine and oxygen radicals showed high reliability.

Metal contamination level will be decreased in order to maintain a device reliability according to device size reduction. Metal contamination from various processes are surveyed. The influence of metal contamination for 7–15nm thick gate oxides is discussed in order to clarify the critical concentration to gate oxides. NIG(Non Intrinsic Gettering) substrates are used in a worst case for gettering. Fe contamination with 4×1010 cm-2 strongly affects the TDDM characteristics, although there is no serious influence in the breakdown voltage even at the concentration of 5×1011 cm-2. The same tendency is observed for Cu contaminant and the critical concentration for TDDB characteristics is around 3×1011 cm-2. High energy B implantation is carried out to form gettering sites near device region. Breakdown voltage and TDDB characteristics are almost the same as epitaxial substrates at Fe concentration up to 1×1012 cm-2. Detailed examination such as SIMS, C-t and DLTS measurements is also supported the effectiveness in high energy gettering.

The present study reviews the use of Cl in gate oxidation furnaces for growth of high quality gate oxides with a thickness in the range of 2 to 15 nm. The following, commercially available, “state of the art” Cl-precursors have been tested: 1,1,1- trichloroethane (TCA), irons-1,2-dichloroethylene (DCE) and oxalyl chloride (OC). Different parameters were evaluated including: metal removal efficiency, poly-silicon haze, Fe bulk incorporation, carrier lifetime and Cl-incorporation in the oxide. Cl2was identified as the active component in Cl-oxidation. As a consequence, OC was identified as being the most efficient Cl-source. In particular, OC is the most suited Cl-source for applications requiring reduced oxygen concentration, such as the manufacturing of ultra thin gate oxides.

Organic adsorbates on silicon wafer surfaces exposed to superclean room air were measured to evaluate organic contamination level of silicon wafers stored in a clean bench up to 180min. Such Si wafers were thermally oxidized and the dielectric degradation behavior were systematically investigated. It is found that a carbon contamination level of half a monolayer influences the charge to quasi-breakdown although the degradation mechanism itself remains unchanged.