Distinct features of amorphous and polycrystalline silicon are attractive for large-area electronics. These features can be utilized in a hybrid structure which consists of both amorphous and polycrystalline silicon materials. For example, an extension of active matrix technology is the integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of the packaging for large-area electronics. This goal can be approached by a combination of amorphous silicon pixel switches and polysilicon drivers. A monolithic fabrication process has been developed based on a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. Another example of the hybrid device structure is a self-aligned amorphous silicon thin film transistor with polysilicon source and drain contacts. The advantages of the self-aligned transistor are reduction of the parasitic capacitance and scaling down of the device dimension. With a selective laser doping technique, self-aligned and shortchannel amorphous silicon thin film transistors have been demonstrated.

We report the first amorphous silicon thin film transistors (TFTs) on flexible, ultra-thin substrates of 25 μm thick stainless steel foil. The transistors remain operational under convex or concave bending down to 2.5 mm radius of curvature. Taking advantage of the flexibility and resiliency of these devices, we have successfully fabricated TFTs using only xerographic toner masks printed directly on to the steel substrate and using mechanical alignment in the laser printer to obtain the necessary overlay accuracy. The goal of our work is to develop a foldable active-matrix transistor backplane, at low cost and high throughput, for use in highly rugged and portable applications such as foldable intelligent maps. Our results suggest that such foldable backplane circuits are feasible.

This article presents mechanisms for low temperature (<150°C) rf plasma enhanced chemical vapor deposition of silicon and silicon nitride thin films that lead to sufficient electronic quality for thin film transistor (TFT) fabrication and operation. For silicon deposition, hydrogen abstraction and etching, and silicon disproportionation reactions are identified that can lead to optimized hydrogen concentration and bonding environments at <150°C. Nitrogen dilution of SiH4/NH3 mixtures during silicon nitride deposition at low temperatures helps promote N-H bonding, leading to reduced charge trapping. Good quality amorphous silicon TFT's fabricated with a maximum processing temperature of 110°C are demonstrated on flexible transparent plastic substrates. Transistors formed with the same process on glass and plastic show linear mobilities of 0.33 and 0.12 cm2/Vs, respectively, with ION/IOFF ratios > 106.

For the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

In order to obtain stable thin-film silicon devices we are conducting research on the implementation of hot-wire CVD amorphous and polycrystalline silicon in thin-film transistors, TFFs. We present results on TFTs with a profiled active layer (deposited at ≥9 Å/s), and correlate the electrical properties with the structure of the silicon matrix at the insulator/semiconductor interface, as determined with cross-sectional transmission electron microscopy. Devices prepared with an appropriate H2 dilution of SiH4 show cone-shaped crystalline inclusions. These crystals start at the interface in some cases, and in others exhibit an 80nm incubation layer prior to nucleation. The crystals in the TFTs with the incubation layer are not cone-shaped, but are rounded off. The hot-wire CVD deposited devices exhibit a high fieldeffect mobility up to 1.5 cm2V−1s−l. Also, these devices have superior stability upon continuous gate bias stress, as compared to conventional glow-discharge α-Si:H TFTs. We ascribe this to a combination of enhanced structural order of the silicon and a low hydrogen content.

Amorphous silicon based thin film transistor liquid crystal displays (TFT/LCD) have become the dominant technology used for flat panel displays for notebook computers. The need for higher resolution, larger diagonal displays for both notebook and desktop applications is discussed. Calculations have shown that the use of high conductivity gate metal such as aluminum or copper, together with the implementation of improved groundrules, can significantly extend today's technology. Aluminum suffers from problems with hillock formation during PECVD processing, and copper typically has poor adhesion to glass, reaction problems with silicon and other PECVD films, and difficulties in contacting it to other metals. Approaches to solving problems with both materials are presented, and a novel reduced mask process to fabricate high resolution, high aperture ratio 10.5” SXGA (1280×1024) displays is described. The process uses copper gate metallurgy with redundancy, without the need for extra processing steps. The resulting displays have 150 dpi color resolution, an aperture ratio of over 35%, and excellent image quality, making them the first high resolution displays that are suitable for notebook applications.

Since being introduced to the production line in 1996, replacing the first generation a-Si TFT line, low-temperature poly-Si production technology aimed at manufacturing small and medium size LCD products has improved steadily corresponding to customers' requirements for rapid growth of the DVC and DSC markets. In the future, this production technology must progress to actual industry technology levels in order to cope with production applied not only to large size displays, which have a major market share in the present display market, but also to a large glass substrate, which effectively cuts the cost of products, although improvement of production yield and productivity in terms of pursuing cost reduction must be proceeded.

This paper has described existing problems of inherent low-temperature poly-Si TFT processes and their relating additional processes in present production methods. We have also discussed updating production technologies. To cope with production for a large size display, it is necessary to establish fabrication technology of higher performance TFTs with electron mobility larger than 200cm2/V·s. We believe that one key technology is to fabricate a large-scale and highly-uniform recrystallized poly-Si film with smooth surface morphology as well as precisely-controlled grain size in production. To cope with production using a large glass substrate, it is essential to develop ELA equipment with laser power greater than 200W.

Photo-leakage-current of poly-Si (polycrystalline Si) TFFs has been investigated by using the rear irradiation OBIC (Optical Beam Induced Current) method. In the case of the offset gate TFIs, it was found that the photo-leakage-current was generated in the offset region of the drain electrode side. In order to reduce the photo-leakage-current, low concentration phosphor (P) was doped in the offset region, which corresponds to LDD (Lightly Doped Drain) structure. In the LDD TFT, the photo leakage current at the offset region decreased remarkably, because of the reduction of hole transportation in this region.

We present a new numerical extraction method for the quasi-static parasitic coupling capacitances associated with geometric overlapping in amorphous silicon (a-Si) thin film transistors (TFTs) and interconnect addressing lines in large-area a-Si imaging systems. The capacitance is extracted using a recently developed computational technique, based on exponential expansion of the Green's function, which offers a quick and accurate means of computing the three-dimensional potential and electric field, and hence, the charge distribution and capacitance. The technique can be used for effectively dealing with the extreme geometry TFT and interconnect structures (where layer thicknesses are much smaller than the other physical dimensions), the floating potential of the glass substrate, and multidielectric media, all of which are typical to large-area a-Si imaging electronics.

The inter-electrode capacitance - voltage (C-V) characteristics of back-channel etched inverted-staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were investigated. It is demonstrated that this simple measurement can be used to diagnose TFT parameters such as the fabricated channel length, the channel resistance, and the error in the mask alignment of the source and drain overlap lengths. The C-V characteristics associated with the hole accumulation in a-Si:H TFTs with n+-type source/drain contacts were also examined. We observed that the a.c. capacitance increases for low frequencies and/or moderately high measurement temperatures provided the gate voltage is sufficiently negative.

In this paper, we present measurement results of stability and leakage current characteristics in inverted staggered hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) for different compositions of the top (passivation) nitride (a-SiNx:H). Here, we varied the deposition parameters, i.e., the ammonia (NH3) to silane (SiH4) gas ratio, of the passivation material for fixed composition of the (nitrogen-rich) gate nitride. When stressed with a prolonged gate bias, the observed shift in both threshold voltage (VT) and leakage current was largest in samples where the gas ratio (R = NH3/SiH4) was small. In the samples considered, R varied from 5 to 25. The shift in VT can be attributed to injection of energetic carriers from the a-Si:H and their subsequent trapping in the top a-SiNx:H layer. The trapping is reduced when the layer is nitrogen-rich.

We present measurements and analysis of a-Si:H thin film transistor (TFT) transients when the gate voltage switches the device from a conducting to a non-conducting state. The drain current transient has been monitored in the medium-long (Ims-100s) time range and exhibits a power law decay extending to at least 10 seconds. The decay has been studied over a range of drain voltages and gate off-state voltages. Measured data show that the gate off-state can help to obtain a low drain leakage current at long times when high drain voltages are being used.

However, the decay at low drain voltages shows little sensitivity to different gate off-state voltages. An analytical model is developed, based on the relaxation of the Fermi level toward mid-gap in a spatially uniform TFT channel. The model shows how deep defects are responsible for the current decay slope at long times, while shallower states determine the slope in the short time range. An energy-independent defect density would produce a 1/t slope for the current decay. Shallow states and deep states affect in opposite ways the slope since their density is energydependent in opposite ways as Fermi level moves deeper into the band-gap. Furthermore, long decay times are associated with a wider depletion region in the channel and increase the total number of defect states involved. A steeper decay than 1/t is expected and observed for shorttime ranges, while a more gradual (about 1/t1/2) one corresponds to long time measurements. The implications of the transient decay for the performance of active matrix arrays will be discussed.

Three dimensional microstructures have been made on glass substrates using surface micromachining techniques. Bridge structures were fabricated using both hydrogenated amorphous silicon and microcrystalline silicon. A low density silicon nitride with an etch rate of 100 Å/s in buffered HF was used as the sacrificial layer. As an example of how micromachining can be applied to large area electronics, thin film transistors (TFT) with the dielectric replaced by an air-gap were fabricated. The electrical characteristics of the first working devices are presented.

We have developed a fully self-aligned amorphous silicon TFT technology, which is suitable for large area image sensors and active matrix displays. Self-alignment is achieved by defining the top nitride by back exposure and then forming source and drain contacts by ionimplantation and silicidation. We incorporate a low resistance gate metallisation process, by using Al metal, capped by Cr. We have compared the process of forming the silicide after the ion-implantation step, with a new process of forming the silicide first and then implanting through the formed silicide. We find a significant advantage to the latter method, where we can achieve a higher doping level and reduced contact resistance. We have therefore optimised our process based on this method. Transistor characteristics as a function of channel length for both methods show the improved contact resistance, obtained with the latter method. We obtain field effect mobilities of 0.7cm2V−1s−1, measured in the saturated region, for a channel length of 8μm.

Two significant developments took place in 1997 in the field of amorphous silicon alloy photovoltaic technology. First, a world record stable cell efficiency of 13% was demonstrated using a spectral-splitting, triple-junction structure. Second, a triple-junction photovoltaic manufacturing facility of an annual capacity of 5 MW was commissioned. In order to make the transition from R&D to production, critical material issues and deposition methods which ensure the lowest module cost per delivered watt needed to be evaluated. In this paper, we discuss some of these issues with special reference to the cell materials.

A new method to analyse the optical and thermal losses in amorphous silicon solar cells is presented. It is demonstrated that PDS measurements can provide important information on the losses that limit the performance of such cells. The major advantage of the method presented is the ability to determine parameters which are not accessible by other methods, i.e. the reflection, absorption without carrier separation, thermalization and losses in p- and n-layer, field losses, recombination and electrical gain of the solar cell under operating conditions. The method can be applied to thin film solar cells of all kinds complementary to DSR which can also be measured in the same set-up. Eliminating some experimental difficulties could lead to a new comprehensive and complementary characterisation method of solar cells of all kinds.

The 70 MHz Plasma Enhance Chemical Vapor Deposition (PECVD) technique has been tested as a high deposition rate (10 A/s) process for the fabrication of a-Si:H and a-SiGe:H alloy ilayers for high efficiency nip solar cells. As a prelude to multi-junction cell fabrication, the deposition conditions used to make single-junction a-Si:H and a-SiGe:H cells using this Very High Frequency (VHF) method have been varied to optimize the material quality and the cell efficiencies. It was found that the efficiencies and the light stability for a-Si:H single-junction cells can be made to remain relatively constant as the i-layer deposition rate is varied from 1 to 10 Å/s. Also these stable efficiencies are similar to those for cells made at low deposition rates (1 Å/s) using the standard 13.56 MHz PECVD technique. For the a-SiGe:H cells of the same i-layer thickness, use of the VHF technique leads to cells with higher currents and an ability to more easily current match triple-junction cells prepared at high deposition rates which should lead to higher multi-junction efficiencies. Thus, use of this VHF method in the production of large area a- Si:H based multi-junction solar modules will allow for higher i-layer deposition rates, higher manufacturing throughput and reduced module cost.

Hydrogen out-diffusion from the n/i interface region plays a major role in controlling the fill factor (FF) and resultant efficiency of n-i-p a-Si:H devices, with the i-layer deposited at high substrate temperatures by the hot wire technique. Modeling calculations show that a thin, highly defective layer at this interface, perhaps caused by significant H out-diffusion and incomplete lattice reconstruction, results in sharply lower device FF's due to the large voltage dropped across this defective layer. One approach to this problem is to introduce trace dopant tailing to ‘compensate’ these defects, but the resultant cells exhibit a poor red response. A second approach involves the addition of buffer layers designed to retard this out-diffusion. We find that an increased H content, either in the n-layer or a thin intrinsic low temperature buffer layer, does not significantly retard this out-diffusion, as observed by secondary ion mass spectrometry (SIMS) H profiles on devices. All these devices have a defect-rich i-layer region near the n/i interface and a poor device efficiency. However, if this low temperature buffer layer is thick enough, the outdiffusion is minimized, yielding nearly flat H profiles and a much improved device performance. We discuss this behavior in the context of the H chemical potentials and H diffusion coefficients in the high temperature, buffer, n-, and stainless steel (SS) substrate layers. The chemical potential differences between the layers control the direction of the H flow and the respective diffusion coefficients, which depend upon many factors such as the local electronic Fermi energy and the extent of the H depletion, determine the rate. Finally, we report a 9.8% initial active area device, fabricated at 16Å/s, using the insights obtained in this study.

We used the internal photoemission technique to determine the exact valence and conduction band offsets at the a-SiC:H/c-Si interface and investigated with numerical simulations their effects on the photocarrier collection in p+a-SiC:H/n c-Si heterojunction solar cells. The valence and conduction band offsets were found to be 0.60 eV and 0.55 eV, respectively. Simulation results show that a high valence band offset increases the open circuit voltage (higher built-in potential) but on the other hand can decrease the fill factor (by blocking the collection of photogenerated holes at the front contact). Interestingly, despite having a large barrier inside the valence band (ΔEv = 0.6 eV), our highly doped p+a-SiC:H/n c-Si heterojunction solar cells show no collection problems (FF= 0.73). Both IPE measurements and simulation results indicate that tunneling of holes through this barrier in the valence band can explain this effect. For thin highly doped (Eact = 0.33 eV) p+a-SiC:H layers, the tunnel barrier becomes very narrow (< 70 Å) and the tunneling probability is strongly enhanced.

The performances of thin film poly-Si solar cells with a thickness of less than 5 μm on a glass substrate have been investigated. The cell of glass / back reflector / n-i-p type Si / ITO is well characterized by the structure of naturally _surface texture and enhanced absorption with a back reflector (STAR), where the active i-type poly-Si layer was fabricated by plasma chemical vapor deposition (CVD) at low temperature. The cell with a thickness of 2.0 μm demonstrated an intrinsic efficiency of 10.7% (aperture 10.1%), the open circuit voltage of 0.539 V and the short current density of 25.8 mA/cm2 as independently confirmed by Japan Quality Assurance. The optical confinement effect explains the excellent spectral response at long wavelength for our cells through the PCID analysis. The higher sensitivity at long-wavelength of our cell appeared in quantum efficiency curves is well correlated to the result of reflectance measurement. The efficiency of 9.3% cell with a thickness of 1.5 pm was proved to be entirely stable with respect to the lightsoaking. Based on the result of various evaluation of diffusion length, it is postulated that the low temperature poly-Si prepared by plasma CVD gives a device quality of poly-Si film.