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Time-Dependent Bias Stress-Induced Instability of SiC MOS Devices

Published online by Cambridge University Press:  01 February 2011

Aivars Lelis
Affiliation:
[email protected], U.S. Army Research Laboratory, SE-DP, 2800 Powder Mill Rd, Adelphi, MD, 20783, United States
Daniel Habersat
Affiliation:
[email protected], U.S. Army Research Laboratory, Adelphi, MD, 20783, United States
Fatimat Olaniran
Affiliation:
[email protected], U.S. Army Research Laboratory, Adelphi, MD, 20783, United States
Brian Simons
Affiliation:
[email protected], U.S. Army Research Laboratory, Adelphi, MD, 20783, United States
James McGarrity
Affiliation:
[email protected], Berkeley Research Associates, Springfield, VA, 22150, United States
F. Barry McLean
Affiliation:
[email protected], Berkeley Research Associates, Springfield, VA, 22150, United States
Neil Goldsman
Affiliation:
[email protected], University of Maryland, Electrical and Computer Engineering, College Park, MD, 20742, United States
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Abstract

We have observed a gate-bias stress induced instability in both the threshold voltage of SiC MOSFETs and the flatband voltage of SiC MOS capacitors. The magnitude of this bias stress-induced instability generally increases linearly with log time, with no saturation of the effect observed, even out to 100,000 seconds. The magnitude also increases with increasing gate field. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with electron tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The effect is repeatable.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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