Hostname: page-component-586b7cd67f-r5fsc Total loading time: 0 Render date: 2024-11-24T19:54:28.404Z Has data issue: false hasContentIssue false
  • English
  • Français

Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking

Published online by Cambridge University Press:  01 February 2011

Takafumi Fukushima ,
Tetsu Tanaka  and
Mitsumasa Koyanagi
Takafumi Fukushima
Affiliation:
[email protected], Tohoku University, United States
Tetsu Tanaka
Affiliation:
[email protected], Tohoku University, Sendai, Japan
Mitsumasa Koyanagi
Affiliation:
[email protected], Tohoku University, Sendai, Japan
Get access

Abstract

We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 micron on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 sec by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.

Keywords

self-assemblyliquidchemical vapor deposition (CVD) (deposition)
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1112: Symposium E – Materials and Technologies for 3-D Integration , 2008 , 1112-E02-07
Copyright
Copyright © Materials Research Society 2009

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Koyanagi, M., Kurino, H., Lee, K.-W., Sakuma, K., Miyakawa, N., and Itani, H., “Future System-on-Silicon LSI Chips,” IEEE MICRO, 18, pp. 17–22, 1998.Google Scholar
2. Matsumoto, T., Satoh, M., Sakuma, K., Kurino, H., Miyakawa, N., Itani, H., and Koyanagi, M., “New Three Dimensional Wafer Bonding Technology Using the Adhesive Injection Method,” Jpn. J. Appl. Phys., 37, pp. 1217–1221, 1998.Google Scholar
3. Igarashi, Y., Morooka, T., Yamada, Y., Nakamura, T, Lee, K.-W., Park, K. T., Kurino, H., and Koyanagi, M., “Filling of Tungsten into Deep Trench Using Time-Modulation CVD Method”, Int. Conf. on Solid State Devices and Materials, pp. 34–35, 2001.Google Scholar
4. Koyanagi, M., Nakamura, T., Yamada, Y., Kikuchi, H., Fukushima, T., Tanaka, T., and Kurino, H., “Three-Dimensional Integration Technology Based on Wafer Bonding with Vertical Buried Interconnections,” IEEE Trans. Electron Devices, 53, pp. 2799–2808, 2006.Google Scholar
5. Kurino, H., Lee, K.-W., Nakamura, T., Sakuma, K., Hashimoto, H., Park, K.-T., Miyakawa, N., Shimazutsu, H., Kim, K.-Y., Inamura, K., and Koyanagi, M., “Intelligent Image Sensor Chip with Three Dimensional Structure,” IEDM Tech. Dig., pp. 879–882, 1999.Google Scholar
6. Lee, K.-W., Nakamura, T., Ono, T., Yamada, Y., Mizukusa, T, Hashimoto, H., Park, K.-T., Kurino, H., and Koyanagi, M., “Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology”, IEDM Tech. Dig., pp. 165–168, 2000.Google Scholar
7. Koyanagi, M., Nakagawa, Y., Lee, K-W., Nakamura, T., Yamada, Y., Inamura, K., Park, K-T., and Kurino, H., “Neuromorphic Vision Chip Fabricated Using Three-Dimensional Integration Technology”, Proc. IEEE Int, Solid State Circuits Conf. (ISSCC), pp. 270–271, 2001.Google Scholar
8. Ono, T., Mizukusa, T., Nakamura, T., Yamada, Y., Igarashi, Y., Morooka, T., Kurino, H. and Koyanagi, M., “Three-Dimensional Processor System Fabricated by Wafer Stacking Technology”, Proc, Int. Symp. on Low-Power and High-Speed Chips (COOL Chips V), pp. 186–193, 2002.Google Scholar
9. Koyanagi, M., “Roadblocks in Achieving Three-Dimensional LSI”, Proc. 8th Symposium on Future Electron Devices, pp. 50–60, 1989.Google Scholar
10. Klumpp, A., Merkel, R., Ramm, P., Weber, J., and Wieland, R., “Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding”, Jpn. J. Appl. Phys., 43, pp. L829–L830, 2004.Google Scholar
11. Fukushima, T., Yamada, Y., Kikuchi, H., and Koyanagi, M., “New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration”, Jpn. J. Appl. Phys., 45, pp. 3030–3035, 2006.Google Scholar
12. Fukushima, T., Yamada, Y., Kikuchi, H., and Koyanagi, M., “New Three-Dimensional Integration Technology Using Self-Assembly Technique”, IEDM Tech. Dig., pp.359–362, 2005.Google Scholar
13. Yeh, H. J. and Smith, J. S., “Fluidic self-assembly for the integration of GaAs light-emitting diodes on Si substrate”, IEEE Photonics Technol. Lett., 6, pp. 706–708, 1994Google Scholar
14. Srinivasan, U., Leipmann, D., and Howe, R. T., “Microstructure to substrate self-assembly using capillary forces“, J. Microelectromechanical Systems, 10, pp. 17–24, 2001.Google Scholar
15. Xiong, X., Hanein, Y., Fang, J., Wang, Y., Wang, W., Schwartz, D. T., and Böhringer, K. F., “Controlled Multibatch Self-Assembly of Microdevices”, J. Microelectromech. Systems, 12, pp. 117–127, 2003.Google Scholar
16. Zheng, W and Jacobs, H. O., “Shape-and-solder-directed self-assembly to package semiconductor device segments”, Appl. Phys. Lett., 85, pp. 3635–3637, 2004.Google Scholar
17. Fukushima, T., Yamada, Y., Kikuchi, H., Konno, T., Liang, J., Ali, A. M., Sasaki, K., Inamura, K., Tanaka, T., and Koyanagi, M., “New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique”, IEDM Tech. Dig., pp. 985–988, 2007.Google Scholar
18. Takahashi, K., Terao, H., Tomita, Y., Yamaji, Y., Hoshino, M., Sato, T., Morifuji, T., Sunohara, M., and Bonkohara, M., “Current Status Research and Development Three-Dimensional Chip Stack Technology”, Jpn. J. Appl. Phys., 40, pp. 3032–3037, 2001.Google Scholar
19. Kawano, M., Takahashi, N., Kurita, Y., Soejima, K., Komuro, M., and Matsui, S., “Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer”, IEEE Trans. Electron Devices, 55, pp. 1014–1620, 2008.Google Scholar