Thermal Management in High-Density, Stacked-Die, Multi-chip Modules

Abstract

Very high density multi-chip modules are being manufactured by tiling an alumina substrate with IC chips and passive components, laminating a film of Kapton over them, laser drilling vias to their I/O pads, and interconnecting them with photo patterned, copper metallization. Additional layers of components and interconnects are added on top of the base layer, as needed, to allow greater integration of large circuits. Current products are typically two layers of chips and seven layers of interconnect. As higher power applications have emerged and the power density of IC chips has increased, thermal management has become a significant factor impacting module design. We have been conducting a thermal modeling effort to map the design space for this technology. Our principal objective is to define and evaluate low thermal impedance (heat removal) configurations for a given chip set. A second objective is to determine what gains in module performance might be realized by improvements in material properties or changes in the relative thicknesses of dielectric and metal layers.