Stress Evolution and Notch Formation During Polysilicon Gate Electrode Etching

Abstract

We have developed a numerical simulation based on the boundary element method that models thermal contraction-induced stresses within semiconductor microstructures, and the effects of these stresses on surface evolution. The test case we have studied is that of polysilicon gate etch during over-etching in a plasma environment. We assume a local etch rate proportional to the normal component of the surface strain energy density gradient caused by the differential thermal contraction of polysilicon substrate and underlying silicon dioxide film. This leads to the prediction of stress-enhanced etching in the area near the polysilicon / gate oxide interface, where large stresses develop during cooling from deposition temperature to room temperature. It is proposed that stress-enhanced etching of this nature may be partially responsible for a common type of deleterious feature observed experimentally during gate electrode patterning known as “notching”.