Hostname: page-component-78c5997874-t5tsf Total loading time: 0 Render date: 2024-11-03T00:30:43.219Z Has data issue: false hasContentIssue false
  • English
  • Français

PVD Ti-Si-N Films Process Development for Copper Interconnect Applications

Published online by Cambridge University Press:  10 February 2011

Jiming Zhang ,
Ram Venkatraman ,
Terri Wilson ,
Robert Fiordalice ,
Rich Gregory  and
Elizabeth Weitzman
Jiming Zhang
Affiliation:
Advanced Products Research and Development Laboratory, Motorola Inc. 3501 Ed Bluestein Blvd., Austin, TX 78721
Ram Venkatraman
Affiliation:
Advanced Products Research and Development Laboratory, Motorola Inc. 3501 Ed Bluestein Blvd., Austin, TX 78721
Terri Wilson
Affiliation:
Advanced Products Research and Development Laboratory, Motorola Inc. 3501 Ed Bluestein Blvd., Austin, TX 78721
Robert Fiordalice
Affiliation:
Advanced Products Research and Development Laboratory, Motorola Inc. 3501 Ed Bluestein Blvd., Austin, TX 78721
Rich Gregory
Affiliation:
MRST, Motorola, Inc.
Elizabeth Weitzman
Affiliation:
Advanced Products Research and Development Laboratory, Motorola Inc. 3501 Ed Bluestein Blvd., Austin, TX 78721
Get access

Abstract

A process has been developed for the deposition of amorphous Ti-Si-N films using reactive ion sputtering of a TiSi target. The Ti-Si-N films have been extensively characterized over a wide range of process parameters. Resistivities of the films less than 300 μΩ-cm have been achieved. Stress measurements on Ti-Si-N films indicate that the film stress changes from tensile to compressive as the nitrogen composition is increased. Near-zero film stresses were achieved by choice of optimum nitrogen N2 flow. SIMS analysis of Cu diffusion through blanket PVD Ti-Si-N (300Å) after an anneal at 390°C/3 hour showed a near overlap of the Cu profile compared to the profile of an unannealed SiO2/PVD Ti-Si-N /Cu film stack, indicating that the Cu did not diffuse significantly through the barrier after anneal. Low contact resistance (0.8 Ω) and low (< 10−11 A) leakage were obtained using a dual inlaid structure with a 300 Å Ti-Si-N processed with optimized conditions. These results showed that Ti-Si-N could be used as a potential barrier for copper metallization.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 514: Symposium I – Advanced Interconnects & Contact Materials & Processes for… , 1998 , 513
Copyright
Copyright © Materials Research Society 1998

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1) Semiconductor Industry Association National Technology Roadmap for Semiconductors, SIA (1993).Google Scholar
2) Wang, S.-Q., MRS Bulletin, vol. XIX, No. 8, p30 (1994).10.1557/S0883769400047710Google Scholar
3) Venkatraman, R. et al. Advanced Metallization and Interconnect Systems for ULSI Applications. (1997).Google Scholar
4) Wang, W., Chang, T., Huang, F., Thin Solid Films, 235, 169 (1993).Google Scholar
5) lijima, T., Shimooka, Y., and Suguro, K., IEEE Trans. Electron, E 79, 568 (1996).Google Scholar