Hostname: page-component-586b7cd67f-r5fsc Total loading time: 0 Render date: 2024-11-24T23:15:15.585Z Has data issue: false hasContentIssue false
  • English
  • Français

Planarization Specification for 22nm and Beyond BEOL CMP

Published online by Cambridge University Press:  01 February 2011

Jihong Choi ,
Changan Wang ,
Yayi Wei ,
Eden Zielinski ,
Wei-tsu Tseng ,
Yongsik Moon ,
Mark Kelling  and
Laertis Economikos
Jihong Choi
Affiliation:
[email protected], GLOBALFOUNDRIES, ASTA/ISDA Alliance, Hopewell Junction, New York, United States
Changan Wang
Affiliation:
[email protected], GLOBALFOUNDRIES, ASTA/ISDA Alliance, Hopewell Junction, New York, United States
Yayi Wei
Affiliation:
[email protected], GLOBALFOUNDRIES, ASTA/ISDA Alliance, Hopewell Junction, New York, United States
Eden Zielinski
Affiliation:
[email protected], GLOBALFOUNDRIES, ASTA/ISDA Alliance, Hopewell Junction, New York, United States
Wei-tsu Tseng
Affiliation:
[email protected], IBM Microelectronics, SRDC, Hopewell Junction, New York, United States
Yongsik Moon
Affiliation:
[email protected], GLOBALFOUNDRIES, ASTA/ISDA Alliance, Hopewell Junction, New York, United States
Mark Kelling
Affiliation:
[email protected], GLOBALFOUNDRIES, ASTA/ISDA Alliance, Hopewell Junction, New York, United States
Laertis Economikos
Affiliation:
[email protected], IBM Microelectronics, SRDC, Hopewell Junction, New York, United States
Get access

Abstract

This study discusses topography specifications for 22 nm and beyond CMP process and presents recent experimental data. We evaluated local topography impact on CD development in the subsequent layer using specially designed 22-nm test patterns. A wide range of localized erosions were generated in CMP within a single exposure field to avoid any focus-correction effect by the scanner or any other scanner-induced focus change between different levels of local erosion. Local erosions were measured by atomic force microscopy (AFM) after each process step from CMP to lithography to identify the local planarization effect from other film coatings between CMP and lithography. Post-litho CD inspection was done in the subsequent layer over the local erosion areas. Using experimental results, the paper also discusses BEOL pattern design rule for maximizing the process window.

Keywords

CMPCulithography (deposition)
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1249: Symposia E/F – Advanced Interconnects and Chemical Mechanical Planarization for Micro-and Nanoelectronics , 2010 , 1249-E01-04
Copyright
Copyright © Materials Research Society 2010

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1International Technology Roadmaps for Semiconductors, 2007 EditionGoogle Scholar
2 Wolf, S., Silicon Processing for the VLSI Era, Volume 2 – Process Integration, Lattice Press, Sunset Beach, CA, 1990 Google Scholar
3 Stein, B., Ouma, D., Divecha, R., Boning, D., Chung, J., Hetherington, D., Harwood, C.R., Nakagawa, O.S. and Oh, S.-Y., IEEE Trans. On Semi. Manuf., 129, 11(1), 1998 Google Scholar
4 Park, T., Tugbawa, T.E. and Boning, D.S., Proc. International Interconnect Techonology Conference, 274, June 2001 Google Scholar
5 Choi, J., Tseng, W., Kim, H., Economikos, L., Fang, Q., Zielinski, E., Engbrecht, E., Child, C., Chae, M., Moon, Y., Proc. of Advanced Metallization Conference 2008, San Diego, CA, 2008, pp 449–455 Google Scholar
6 Steigerwald, J., Zirpoli, R., Murarka, S., Price, D. and Gutmann, R., J. Electrochem. Soc., 141 (10), 2842, 1994 Google Scholar
7 Nuyen, V., Velden, P. Van der, Daamen, R., Kranenburg, H. Van and Woerlee, P., 46th Annual IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 11, 2000 Google Scholar
8 Yang, L., Solid State Technology, 111, June 2000 Google Scholar