Performance of Polycrystalline Silicon Thin Film Transistors with Double Layer Gate Dielectric

Abstract

The electrical characteristics of n- and p-channel poly-Si thin film transistors having a double layer gate dielectric structure are reported. The gate dielectric consists of a silicon dioxide layer and a nitrogen-rich silicon nitride layer, both deposited by PECVD at low temperatures (≥400° C). When the silicon nitride was in contact with the poly-Si film, the effective carrier mobility (μ_eff), threshold voltage (V_th and subthreshold swing (S_t) for n-channel devices were 36 cm²/Vsec, -1.8 V and 1.65 V/decade, respectively, while for p-channel devices were 6 cm²/Vsec, -37 and 2.47 V/decade, respectively. These devices were not stable under negative gate bias stress, due to the injection of holes into the silicon nitride. When silicon dioxide was in contact with the poly-Si film, the μ_eff, V_th and S_t for n-channel devices were 26 cm₂/Vsec, 3 V and 1.63 V/decade, respectively, while for p-channel devices were 10 cm₂/Vsec, -22 V and 1.52 V/decade, respectively. These devices were stable under d.c. bias stress.