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Optimised Multi-Scan H-Beam Annealing Of Mos Devices

Published online by Cambridge University Press:  15 February 2011

C J Pollard
Affiliation:
British Telecommunications Research Laboratories, Martlesham Heath, Ipswich, Suffolk, IP5 7RE, England
A E Glaccum
Affiliation:
British Telecommunications Research Laboratories, Martlesham Heath, Ipswich, Suffolk, IP5 7RE, England
J D Speight
Affiliation:
British Telecommunications Research Laboratories, Martlesham Heath, Ipswich, Suffolk, IP5 7RE, England
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Abstract

The optimum e-beam anneal conditions for damage free wafer annealing, implant activation uniformity across 3 inch wafers and low dose boron activation have been investigated with reference to the needs of MOS device processing. Some effects of e-beam annealing on MOS gate dielectrics are reported.

Type
Research Article
Copyright
Copyright © Materials Research Society 1982

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References

REFERENCES

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