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Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects

Published online by Cambridge University Press:  01 February 2011

Aditya Pradeep Karmarkar ,
Xiaopeng Xu ,
Xiao Lin ,
Greg Rollins ,
Victor Moroz  and
Xi-Wei Lin
Aditya Pradeep Karmarkar
Affiliation:
[email protected], Synopsys (India) Private Limited, TCAD DFM Solutions, My Home Tycoon, 4th Floor, Block A,, Begumpet, Hyderabad, 500016, India, +91-40-40331536, +91-40-40133770
Xiaopeng Xu
Affiliation:
[email protected], Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Xiao Lin
Affiliation:
[email protected], Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Greg Rollins
Affiliation:
[email protected], Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Victor Moroz
Affiliation:
[email protected], Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
Xi-Wei Lin
Affiliation:
[email protected], Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043, United States
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Abstract

With decreasing feature sizes for every technology node, multi-level metallization schemes that employ copper interconnects and low-k dielectrics are required to achieve the requisite circuit performance. Here, the effects of the mechanical stresses originating from the packaging process on Cu/Low-k interconnects are assessed. The impact of package defects on interconnect reliability is also analyzed. It is seen that the package reliability varies with underfill mechanical properties. The packaging process introduces global level stresses that propagate to the local, i.e. interconnect, level. Moreover, the package defects also have an adverse impact on the mechanical stresses in the metallization structure. The package defects alter the mechanical stresses in the metal lines and affect the reliability. The complex interaction between packaging process induced stresses, package level defects and mechanical properties of various materials is analyzed in order to create robust interconnect designs.

Keywords

packagingthermal stressesstress/strain relationship
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1079: Symposium N – Materials and Processes for Advanced Interconnects for Microelectronics , 2008 , 1079-N09-09
Copyright
Copyright © Materials Research Society 2008

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References

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