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Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs

Published online by Cambridge University Press:  15 June 2012

Shuu’ichirou Yamamoto ,
Yusuke Shuto  and
Satoshi Sugahara
Shuu’ichirou Yamamoto
Affiliation:
Department of Information Processing, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8502, Japan CREST, Japan Science and Technology Agency, 4-1-8 Hon-cho, Kawaguchi 332-0012, Japan
Yusuke Shuto
Affiliation:
Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8503, Japan CREST, Japan Science and Technology Agency, 4-1-8 Hon-cho, Kawaguchi 332-0012, Japan
Satoshi Sugahara
Affiliation:
Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8503, Japan CREST, Japan Science and Technology Agency, 4-1-8 Hon-cho, Kawaguchi 332-0012, Japan
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Abstract

We proposed and computationally analyzed a nonvolatile power-gating field programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power-gating (PG). Break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET were proposed, which allows highly efficient PG operations with a fine granularity.

Keywords

devicesmemorymagnetoresistance (transport)
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1430: Symposium E – Materials and Physics of Emerging Nonvolatile Memories , 2012 , mrss12-1430-e04-10
Copyright
Copyright © Materials Research Society 2012

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References

REFERENCES

1. Xilinx, http://www.xilinx.com/ Google Scholar
2. Yamamoto, S., Shuto, Y. and Sugahara, S., 71st Autumn Meet. Jpn. Soc. Appl. Phys. (2010) paper 16a-A-2.Google Scholar
3. Yamamoto, S. and Sugahara, S., Jpn. J. Appl. Phys. 48, 043001 (2009).Google Scholar
4. Shuto, Y., Yamamoto, S. and Sugahara, S., J. Appl. Phys. 105, 07C933 (2009) .Google Scholar
5. Yamamoto, S., Shuto, Y. and Sugahara, S., Jpn. J. Appl. Phys. 49, 090204 (2010).Google Scholar
6. Yamamoto, S., Shuto, Y. and Sugahara, S., Electronics Lett. 47, 1027 (2011).Google Scholar
7. Hayakawa, J., Ikeda, S., Matsukura, F., Takahashi, H., and Ohno, H., Jpn. J. Appl. Phys. 44, L587(2005).Google Scholar
8. Berkeley Predictive Technology Model, http://www.eas.asu.edu/∼ptm.Google Scholar
9. Shuto, Y., Yamamoto, S. and Sugahara, S., Jpn. J. Appl. Phys. 51, 040212 (2012).Google Scholar
10. Shuto, Y., Yamamoto, S. and Sugahara, S., 2012 4th IEEE International Memory Workshop (2012).Google Scholar
11. Zhao, W. et al. ., ACM Trans. Embedded Comp. Sys. 9 (2009) Article 14.Google Scholar
12. Suzuki, D. et al. ., 2009 Symp. VLSI Circuits Dig. Tech. Papers (2009) p.80.Google Scholar
13. Xilinx, Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010, p.190.Google Scholar