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Mechanisms of Stacking Fault Growth in SiC PiN Diodes

Published online by Cambridge University Press:  15 March 2011

R. E. Stahlbush ,
M. E. Twigg ,
J. J. Sumakeris ,
K. G. Irvine  and
P. A. Losee
R. E. Stahlbush
Affiliation:
Naval Research Laboratory, Washington, DC 20374, USA
M. E. Twigg
Affiliation:
Naval Research Laboratory, Washington, DC 20374, USA
J. J. Sumakeris
Affiliation:
Cree, Inc., Durham, NC 27703, USA
K. G. Irvine
Affiliation:
Cree, Inc., Durham, NC 27703, USA
P. A. Losee
Affiliation:
Rensselaer Polytechnic Institute, Troy, NY 12180, USA
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Abstract

The early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150μm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 μm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials' line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 815 , 2004 , J6.4
Copyright
Copyright © Materials Research Society 2004

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