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Integration of NiSi SALICIDE for Deep Submicron CMOS Technologies

Published online by Cambridge University Press:  10 February 2011

X. W. Lin ,
N. Ibrahim ,
L. Topete  and
D. Pramanik
X. W. Lin
Affiliation:
VLSI Technology, Inc. 1109 McKay Drive, San Jose, CA 95131
N. Ibrahim
Affiliation:
Stanford University, Center for Integrated Systems, Stanford, CA 94305
L. Topete
Affiliation:
VLSI Technology, Inc. 1109 McKay Drive, San Jose, CA 95131
D. Pramanik
Affiliation:
VLSI Technology, Inc. 1109 McKay Drive, San Jose, CA 95131
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Abstract

A NiSi-based self-aligned silicidation (SALICIDE) process has been integrated into a 0.25 Ion CMOS technology. It involves rapid thermal annealing (RTA) of Ni thin films (300, Å thick) on Si substrates in the temperature range ≈400 - 700 °C. It was found that the NiSi sheet resistance (Rs) gradually decreases with decreasing linewidth. Parameters, such as RTA temperature, substrate dopant (As vs BF2) and structure (single crystal vs poly), were found to have little effects on Rs. NiSi forms a smoother interface with single crystalSi than with poly Si, and has a slightly lower resistivity. MOSFETs based on NiSi show comparable device characteristics to those obtained with Ti SALICIDE. Upon thermal annealing, NiSi remains stable at 450 °C for more than 39 hours. The same is true for 500 °C anneals up to 6 hours, except for NiSi narrow lines (<0.5 μm) on n+ poly Si substrates whose Rs is moderately increased after a 6 hr anneal. This work demonstrates that with an appropriate low-thermal budget backend process, NiSi SALICIDE can be a viable process for deep submicron ULSI technologies.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 514: Symposium I – Advanced Interconnects & Contact Materials & Processes for… , 1998 , 179
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

1. Maex, K., Mater. Sci. Eng. R11, 53 (1993).Google Scholar
2. Kittl, J.A. et al., Future Fab International 2, 191 (1997).Google Scholar
3. Ohguro, T. et al., IEEE Electron Dev. 41, 2305 (1994).10.1109/16.337443Google Scholar
4. Morimoto, T. et al. IEEE Electron Dev. 42, 915 (1995).Google Scholar
5. Xu, D.-X. et al., Mat. Res. Soc. Symp. Proc. 404, 59 (1996).Google Scholar
6. Xu, D.-X., Das, S.R., Peters, C.J., and Erickson, L.E., (to be published).Google Scholar
7. Bothra, S. et al., Proc. VLSI Multilevel Interconnect Conf (1997) p. 43.Google Scholar
8. Qian, L.Q. et al., Proc. VLSI Multilevel Interconnect Conf (1997) p. 615.Google Scholar