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Influence of Voed Geometry on Electromigration Failure in Via-Line Structures

Published online by Cambridge University Press:  10 February 2011

B. Miner ,
T. S. Sriram ,
A. Pelillo  and
S. A. Bill
B. Miner
Affiliation:
Digital Semiconductor (a business unit of Digital Equipment Corporation), Hudson, MA 01749
T. S. Sriram
Affiliation:
Digital Semiconductor (a business unit of Digital Equipment Corporation), Hudson, MA 01749
A. Pelillo
Affiliation:
Digital Semiconductor (a business unit of Digital Equipment Corporation), Hudson, MA 01749
S. A. Bill
Affiliation:
Digital Semiconductor (a business unit of Digital Equipment Corporation), Hudson, MA 01749
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Abstract

We present in this work a series of detailed failure analyses of via-line structures to correlate void geometry and resistance behavior during accelerated electromigration testing. We find that while the void volume is dependent only on the time under stress, the resistance change is affected very strongly by void geometry and location. The primary effect of void location and geometry is to determine the availability of alternate current paths and how soon during the test these come into effect. The microstructure and crystallography of the connecting Al lines appears to play a secondary role in determining which samples fail early. The processing of small geometry vias can lead to high resistance interfaces between the via and underlying metal which can lead to large variations in electromigration lifetime depending on void geometry and location.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 473: Symposium J – Materials Reliability in Microelectronics VII , 1997 , 351
Copyright
Copyright © Materials Research Society 1997

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References

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